Abstract: A semiconductor memory device has a semiconductor substrate, a peripheral circuit region and a memory cell region on the principal surface of the semiconductor substrate. The semiconductor memory device has a first well formed in the peripheral circuit region, a second well of first conductivity type and a third well of second conductivity type formed in the memory cell region having substantially the same depth, and a device element isolator formed in the memory cell region for isolating a device element formed in the second well from a device element formed in the third well. The second and third wells extend to an area under the device element isolator. The second and third wells extend to a level under the device element isolator. The second and third wells may include a first layer having a depth shallower than the first well, and a second layer having substantially the same depth as the first well.

Abstract: First and second gate electrode layers that are positioned in a first conductive layer, first and second drain-drain contact layers that are positioned in a second conductive layer, and first and second drain-gate contact layers that are positioned in a third conductive layer together form conductive layers for a flip-flop. A sub word line extends in the X-axis direction in the first conductive layer. A VDD wire is disposed extending in the X-axis direction in the second conductive layer. A main word line is disposed extending in the X-axis direction in the third conductive layer. A bit line, a bit line/, a VSS wire, and a VDD wire are disposed extending in the Y-axis direction in the fourth conductive layer.

Abstract: A memory cell of an SRAM has a structure including five conductive layers over a field. A gate-gate electrode layer including gate electrodes of a driver transistor and a load transistor is located in a first conductive layer. A drain-drain connecting layer connecting a drain of a driver transistor with a drain of a load transistor and including tungsten is located in a second conductive layer. A drain-gate connecting layer connecting the drain-drain connecting layer with the gate-gate electrode layer is located in a third conductive layer. A first-layer/third-layer stacked contact-conductive section is used to connect the gate-gate electrode layer with the drain-gate connecting layer.

Abstract: A method and apparatus to enable a user to easily make a search with respect to a large amount of music data copied and stored from CDs in a built-in recording medium. A music server is able to record a large amount of music data played back from CDs in a built-in hard disk drive (HDD). When recording the music data, table of contents (TOC) information of each CD is read out of the CD and recorded in the HDD, and simultaneously sent to a personal computer via a connecting line. A CD album information database is provided in the form of a CD-ROM to the personal computer. In the personal computer, which one of CDs recorded in the database on the CD-ROM corresponds to the relevant CD is searched based on the total playing time and the time information of each track which are contained in the TOC information sent to the personal computer. A search result is sent back to the music server.

Abstract: The drain of a drive transistor Q3 and the drain of a load transistor Q5 are connected by a first drain—drain contact layer. The drain of a drive transistor Q4 and the drain of a load transistor Q6 are connected by a second drain—drain contact layer. The gate electrodes of the drive transistor Q3 and the load transistor Q5 (a first gate electrode layer) are connected to the second drain—drain contact layer by a first drain-gate contact layer. The gate electrodes of the drive transistor Q4 and the load transistor Q6 (a second gate electrode layer) are connected to the first drain—drain contact layer by a second drain-gate contact layer.

Abstract: A semiconductor device having an SRAM section in which a p-well, a first n-well, and a second n-well are formed in a semiconductor substrate. Two n-type access transistors and two n-type driver transistors are formed in the p-well. Two p-type load transistors are formed in the first n-well. The second n-well is located under the p-well and the first n-well and also is connected to the first n-well. The potential of the first n-well is supplied from the second n-well. According to the present invention, the SRAM section can be reduced in size.

Abstract: A method and apparatus to enable a user to easily make a search with respect to a large amount of music data copied and stored from CDs in a built-in recording medium. A music server is able to record a large amount of music data played back from CDs in a built-in hard disk drive (HDD). When recording the music data, table of contents (TOC) information of each CD is read out of the CD and recorded in the HDD, and simultaneously sent to a personal computer via a connecting line. A CD album information database is provided in the form of a CD-ROM to the personal computer. In the personal computer, which one of CDs recorded in the database on the CD-ROM corresponds to the relevant CD is searched based on the total playing time and the time information of each track which are contained in the TOC information sent to the personal computer. A search result is sent back to the music server.

Abstract: A communication system includes a first storage section for storing a plurality of pieces of contents information, a second storage section for storing a plurality of pieces of contents information, a control section for accessing the contents information stored in the first storage section and the second storage section based on a single set of management information for managing the contents information stored in the first storage section and the second storage section, a communication section for interconnecting the first storage section, the second storage section and the control section for communication, and an accounting setting section for setting an amount of money to be imposed on a predetermined user in response to use of the first storage section or the second storage section.

Abstract: The positions of first terminals of a first semiconductor chip have a plane symmetrical relationship with the positions of second terminals of a second semiconductor chip. First buffer circuits of the first semiconductor chip are identical with second buffer circuits of the second semiconductor chip at least in design. First and second internal circuits are identical with each other at least in design. The first and second semiconductor chips have different interconnecting lines.

Abstract: A chemical mechanical polishing apparatus includes a pad conditioner having a conditioner head, a cleaning cup for receiving and cleaning the conditioner head of the pad conditioner, and a fluid dispenser for dispensing a cleaning fluid onto the conditioner head.

Abstract: The invention provides SRAMs that can reduce memory cells in size and correct light proximity effect. Gate electrode layers in a first layer, drain-drain connection layers in a second layer, and drain-gate connection layers in a third layer define connection wirings of a flip-flop. A p+ type well contact region is provided for every two of the memory cells arranged in the Y-axis direction.

Abstract: The invention provides SRAMs that can reduce memory cells in size and correct light proximity effect. Gate electrode layers in a first layer, drain-drain connection layers in a second layer, and drain-gate connection layers in a third layer define conduction layers of a flip-flop. A source contact layer of load transistors are located adjacent end sections of the gate electrode layers, and both of the end sections bend outwardly to avoid contact with the source contact layer.

Abstract: A semiconductor memory device comprising first and second gate electrode layers in a first conductive layer, first and second drain-drain connecting layers in a second conductive layer, and first and second drain-gate connecting layers in a third conductive layer. The first and second drain-gate connecting layers are located higher than the first and second gate electrode layers. Therefore, a source contact layer can be located in the region between gate electrode layers while preventing a contact with the second drain-gate connecting layer.

Abstract: A semiconductor memory device has a silicon substrate 10. A first embedded layer 11 is formed in the silicon substrate 10 under a p-well 18 in an area below a region where a drain 36 of a driver transistor 30 is located. The first embedded layer 11 makes a junction with the p-well 18. Also, the first embedded layer 11 is formed below an n-well 16 and contacts the n-well 16. When the drain 36 of the driver transistor 30 is at a voltage of 3V, &agr;-ray may pass through the p-well 18, the first embedded layer 11 and the silicon substrate 10. As a result, electron-hole pairs are cut. Due to the presence of the p-n junction that is formed by the p-well 18 and the first embedded layer 11, only electrons in the p-well 18 are drawn to the drain 36. As a result, a fall in the drain voltage of 3V is reduced. As a consequence, the device structure makes it difficult to destroy retained data.

Abstract: A semiconductor device has a semiconductor substrate having a peripheral circuit area and a memory cell area. A border region having a well of a first conductivity is formed between the peripheral circuit area and the memory cell area. A well of a second conductivity is formed in the peripheral circuit area. The well in the peripheral circuit area is in contact with the border region but not in contact with the memory cell area. Dummy transistors are formed in the border region. The dummy transistors are arranged with substantially the same transistor forming density as that of the memory cell area.

Abstract: The invention provides SRAMs that can reduce memory cells in size and correct light proximity effect. Gate electrode layers in a first layer, drain-drain connection layers in a second layer, and drain-gate connection layers in a third layer define conduction layers of a flip-flop. The drain-gate connection layer has an extension section extending in a direction toward the drain-gate connection layer. The drain-gate connection layer 41b has an extension section extending in a direction toward the drain-gate connection layer.

Abstract: The invention provides SRAMs that can reduce memory cells in size and correct light proximity effect. Gate electrode layers in a first layer, drain-drain connection layers in a second layer, and drain-gate connection layers in a third layer define conduction layers of a flip-flop. Driver transistors of one memory cell do not commonly share the n+ type source region with driver transistors of another memory cell.

Abstract: A semiconductor memory device has a silicon substrate 10. A first embedded layer 11 is formed in the silicon substrate 10 under a p-well 18 in an area below a region where a drain 36 of a driver transistor 30 is located. The first embedded layer 11 makes a junction with the p-well 18. Also, the first embedded layer 11 is formed below an n-well 16 and contacts the n-well 16. When the drain 36 of the driver transistor 30 is at a voltage of 3V, &agr;-ray may pass through the p-well 18, the first embedded layer 11 and the silicon substrate 10. As a result, electron-hole pairs are cut. Due to the presence of the p-n junction that is formed by the p-well 18 and the first embedded layer 11, only electrons in the p-well 18 are drawn to the drain 36. As a result, a fall in the drain voltage of 3V is reduced. As a consequence, the device structure makes it difficult to destroy retained data.

Abstract: The drain of a drive transistor Q3 and the drain of a load transistor Q5 are connected by a first drain-drain contact layer. The drain of a drive transistor Q4 and the drain of a load transistor Q6 are connected by a second drain-drain contact layer. The gate electrodes of the drive transistor Q3 and the load transistor Q5 (a first gate electrode layer) are connected to the second drain-drain contact layer by a first drain-gate contact layer. The gate electrodes of the drive transistor Q4 and the load transistor Q6 (a second gate electrode layer) are connected to the first drain-drain contact layer by the second drain-gate contact layer.

Abstract: A semiconductor device has a semiconductor substrate having a peripheral circuit area and a memory cell area. A border region having a well of a first conductivity is formed between the peripheral circuit area and the memory cell area. A well of a second conductivity is formed in the peripheral circuit area. The well in the peripheral circuit area is in contact with the border region but not in contact with the memory cell area. Dummy transistors are formed in the border region. The dummy transistors are arranged with substantially the same transistor forming density as that of the memory cell area.