Abstract: A communication system includes a first storage section for storing a plurality of pieces of contents information, a second storage section for storing a plurality of pieces of contents information, a control section for accessing the contents information stored in the first storage section and the second storage section based on a single set of management information for managing the contents information stored in the first storage section and the second storage section, a communication section for interconnecting the first storage section, the second storage section and the control section for communication, and an accounting setting section for setting an amount of money to be imposed on a predetermined user in response to use of the first storage section or the second storage section.

Abstract: A communication system includes a first storage section for storing pieces of content information, a second storage section for also storing pieces of content information, a control section for accessing the content information stored in the first storage section and the second storage section based on a single set of management information for managing the content information stored in the first storage section and the second storage section, a communication section for interconnecting the first storage section, the second storage section and the control section for communication, and an account setting section for setting an amount of a fee to be imposed on a predetermined user in response to use of the first storage section or the second storage section.

Abstract: To provide a reproduction apparatus able to easily select a desired content data based on an attribute of the content data by a simple operation from a user and a reproduction method for the same, wherein the reproduction apparatus having: a display displaying the item; a first operation unit instructing a switch of the attribute; a second function unit instructing a selection of a predetermined item on the display; and a processing unit switching a first screen from a screen of a plurality of items so as to display a plurality of items when the first operation key is operated, and switching to a second screen displaying a plurality of item when the second operation key is operated when a plurality of item is displayed on the first screen.

Abstract: A communication system includes a terminal having a first storage section for storing a number of pieces of content information, a second storage section for storing a number of pieces of the content information, a storage control section for placing a content ID stored in the second storage section into purchase information for each terminal and stored in the second storage section, an access control section for controlling access to the content information corresponding to the content ID stored in the second storage section, and an accounting setting section for setting an amount of a fee to be imposed on the terminal in response to the purchase information.

Abstract: The present invention relates to a packet transfer unit, which comprises a search key memory that stores a search key for a transfer destination of a packet and verification information generated from the search key, in association with a storage location of transfer information memorized in a transfer information memory, wherein a transfer information acquisition unit searches the search key memory by using the search key generated based on the header information and the verification information generated from the search key, acquires storage location information of the transfer information from the search key memory when a match with the search key and the verification information memorized in the search key memory is found, and acquires the transfer information stored in the transfer information memory based on the acquired storage location information, and wherein a transfer unit transfers the packet based on the acquired transfer information.

Abstract: The invention provides methods of reducing the severity of a proliferative disorder. One method involves administering to an individual having the proliferative disorder an effective amount of paricalcitol, wherein the paricalcitol reduces cellular proliferation, with the proviso that the cancer is not prostate cancer or head and neck squamous cell carcinoma. Another method of reducing the severity of a proliferative disorder provided by the invention involves administering to an individual having the proliferative disorder an effective amount of paricalcitol and an anti-cancer agent, wherein the combination of paricalcitol and the anti-cancer agent reduces cell proliferation, with the proviso that the proliferative disorder is not prostate cancer or head and neck squamous cell carcinoma.

Abstract: A semiconductor device includes an SRAM section and a logic circuit section formed on a single semiconductor substrate. First and second gate electrode layers located in a first conductive layer, first and second drain-drain contact layers located in a second conductive layer, first and second drain-gate contact layers located in a third conductive layer become conductive layers for forming a flip-flop of the SRAM section. The logic circuit section has no wiring layer at the same level as the first and second drain-drain contact layers.

Abstract: A semiconductor device having an SRAM section in which a p-well, a first n-well, and a second n-well are formed in a semiconductor substrate. Two n-type access transistors and two n-type driver transistors are formed in the p-well. Two p-type load transistors are formed in the first n-well. The second n-well is located under the p-well and the first n-well and also is connected to the first n-well. The potential of the first n-well is supplied from the second n-well. According to the present invention, the SRAM section can be reduced in size.

Abstract: The present invention provides a semiconductor device including a first gate—gate electrode layer located in a first conductive layer and including gate electrodes of a first load transistor and a first driver transistor and a second gate—gate electrode layer located in the first conductive layer and including gate electrodes of a second load transistor and a second driver transistor. A first drain—drain connecting layer is located in a second conductive layer which is an upper layer of the first conductive layer and connects a drain of the first load transistor with a drain of the first driver transistor. A second drain—drain connecting layer is located in the second conductive layer and connects a drain of the second load transistor with a drain of the second driver transistor.

Abstract: The positions of first terminals of a first semiconductor chip have a plane symmetrical relationship with the positions of second terminals of a second semiconductor chip. First buffer circuits of the first semiconductor chip are identical with second buffer circuits of the second semiconductor chip at least in design. First and second internal circuits are identical with each other at least in design. The first and second semiconductor chips have different interconnecting lines.

Abstract: The invention provides SRAMs that can reduce memory cells in size and correct light proximity effect. Gate electrode layers in a first layer, drain—drain connection layers in a second layer, and drain-gate connection layers in a third layer define conduction layers of a flip-flop. The drain-gate connection layer has an extension section extending in a direction toward the drain-gate connection layer. The drain-gate connection layer 41b has an extension section extending in a direction toward the drain-gate connection layer.

Abstract: The invention provides SRAMs that can reduce memory cells in size and correct light proximity effect. Gate electrode layers in a first layer, drain—drain connection layers in a second layer, and drain-gate connection layers in a third layer define conduction layers of a flip-flop. Driver transistors of one memory cell do not commonly share the n+ type source region with driver transistors of another memory cell.

Abstract: A semiconductor memory device (SRAM) comprises memory cells, each of which includes two load transistors, two driver transistors and two transfer transistors. The SRAM cell includes a semiconductor substrate in which the transistors are formed, a first interlayer dielectric formed on the semiconductor substrate, first contact portions formed in the first interlayer dielectric and first wiring layers (node wiring layers and pad layers) formed on the first interlayer dielectric. The first contact portions and the first wiring layers include metal layers made of refractory metal and a refractory metal nitride layers. This semiconductor memory device of the present invention is capable of enhancing an integration degree of wiring layers and achieving a microfabrication.

Abstract: A method and apparatus to enable a user to easily make a search with respect to a large amount of music data copied and stored from CDs in a built-in recording medium. A music server is able to record a large amount of music data played back from CDs in a built-in hard disk drive (HDD). When recording the music data, table of contents (TOC) information of each CD is read out of the CD and recorded in the HDD, and simultaneously sent to a personal computer via a connecting line. A CD album information database is provided in the form of a CD-ROM to the personal computer. In the personal computer, which one of CDs recorded in the database on the CD-ROM corresponds to the relevant CD is searched based on the total playing time and the time information of each track which are contained in the TOC information sent to the personal computer. A search result is sent back to the music server.

Abstract: A semiconductor device includes an SRAM section and a logic circuit section formed on a single semiconductor substrate. First and second gate electrode layers located in a first conductive layer, first and second drain-drain contact layers located in a second conductive layer, first and second drain-gate contact layers located in a third conductive layer become conductive layers for forming a flip-flop of the SRAM section. The logic circuit section has no wiring layer at the same level as the first and second drain-drain contact layers.

Abstract: The invention provides SRAMs that can reduce memory cells in size and correct light proximity effect. Gate electrode layers in a first layer, drain-drain connection layers in a second layer, and drain-gate connection layers in a third layer define connection wirings of a flip-flop. A p+ type well contact region is provided for every two of the memory cells arranged in the Y-axis direction.

Abstract: A semiconductor memory device has a silicon substrate 10. A first embedded layer 11 is formed in the silicon substrate 10 under a p-well 18 in an area below a region where a drain 36 of a driver transistor 30 is located. The first embedded layer 11 makes a junction with the p-well 18. Also, the first embedded layer 11 is formed below an n-well 16 and contacts the n-well 16. When the drain 36 of the driver transistor 30 is at a voltage of 3V, &agr;-ray may pass through the p-well 18, the first embedded layer 11 and the silicon substrate 10. As a result, electron-hole pairs are cut. Due to the presence of the p-n junction that is formed by the p-well 18 and the first embedded layer 11, only electrons in the p-well 18 are drawn to the drain 36. As a result, a fall in the drain voltage of 3V is reduced. As a consequence, the device structure makes it difficult to destroy retained data.

Abstract: First and second gate electrode layers located in a first conductive layer, first and second drain-drain connecting layers located in a second conductive layer, and first and second drain-gate connecting layers located in a third conductive layer become conductive layers for forming a flip-flop. First and second contact-conductive sections are formed in a region from an interlayer dielectric between the first and second conductive layers to an interlayer dielectric between the second and third conductive layers. The first drain-gate connecting layer is connected to the second gate electrode layer with the first contact-conductive section interposed. The second drain-gate connecting layer is connected to the first gate electrode layer with the second contact-conductive section interposed.

Abstract: A semiconductor device has a semiconductor substrate having a peripheral circuit area and a memory cell area. A border region having a well of a first conductivity is formed between the peripheral circuit area and the memory cell area. A well of a second conductivity is formed in the peripheral circuit area. The well in the peripheral circuit area is in contact with the border region but not in contact with the memory cell area. Dummy transistors are formed in the border region. The dummy transistors are arranged with substantially the same transistor forming density as that of the memory cell area.

Abstract: The invention provides SRAMs that can reduce memory cells in size and correct light proximity effect. Gate electrode layers in a first layer, drain-drain connection layers in a second layer, and drain-gate connection layers in a third layer define conduction layers of a flip-flop. A source contact layer of load transistors are located adjacent end sections of the gate electrode layers, and both of the end sections bend outwardly to avoid contact with the source contact layer.