Patents by Inventor Takashi Miida

Takashi Miida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9214242
    Abstract: In a programming method for a NAND flash memory device, a self-boosting scheme is used to eliminate excess electrons in the channel of an inhibit cell string that would otherwise cause programming disturb. The elimination is enabled by applying a negative voltage to word lines connected to the inhibit cell string before boosting the channel, and this leads to bringing high program immunity. A row decoder circuitry to achieve the programming operation and a file system architecture based on the programming scheme to improve the efficiency of file management are also described.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: December 15, 2015
    Assignees: POWERCHIP CORPORATION, POWERCHIP TECHNOLOGY CORPORATION
    Inventors: Takashi Miida, Riichiro Shirota, Hideki Arakawa, Ching Sung Yang, Tzung Ling Lin
  • Publication number: 20140140129
    Abstract: In a programming method for a NAND flash memory device, a self-boosting scheme is used to eliminate excess electrons in the channel of an inhibit cell string that would otherwise cause programming disturb. The elimination is enabled by applying a negative voltage to word lines connected to the inhibit cell string before boosting the channel, and this leads to bringing high program immunity. A row decoder circuitry to achieve the programming operation and a file system architecture based on the programming scheme to improve the efficiency of file management are also described.
    Type: Application
    Filed: November 15, 2013
    Publication date: May 22, 2014
    Applicants: Powerchip Technology Corporation, Powerchip Corporation
    Inventors: Takashi MIIDA, Riichiro SHIROTA, Hideki ARAKAWA, Ching Sung YANG, Tzung Ling LIN
  • Patent number: 8599614
    Abstract: In a programming method for a NAND flash memory device, a self-boosting scheme is used to eliminate excess electrons in the channel of an inhibit cell string that would otherwise cause programming disturb. The elimination is enabled by applying a negative voltage to word lines connected to the inhibit cell string before boosting the channel, and this leads to bringing high program immunity. A row decoder circuitry to achieve the programming operation and a file system architecture based on the programming scheme to improve the efficiency of file management are also described.
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: December 3, 2013
    Assignees: Powerchip Corporation, Powerchip Technology Corporation
    Inventors: Takashi Miida, Riichiro Shirota, Hideki Arakawa, Ching Sung Yang, Tzung Ling Lin
  • Patent number: 8334164
    Abstract: An image sensor has a substrate, a dielectric layer positioned on the substrate, a pixel array including a plurality of pixels defined on the substrate, a shield electrode positioned between any two adjacent pixel electrodes of the pixels, a photo conductive layer positioned on the shield electrode and the pixel electrodes, and a transparent conductive layer covering the photo conductive layer.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: December 18, 2012
    Assignee: Powerchip Technology Corporation
    Inventor: Takashi Miida
  • Publication number: 20110310666
    Abstract: In a programming method for a NAND flash memory device, a self-boosting scheme is used to eliminate excess electrons in the channel of an inhibit cell string that would otherwise cause programming disturb. The elimination is enabled by applying a negative voltage to word lines connected to the inhibit cell string before boosting the channel, and this leads to bringing high program immunity. A row decoder circuitry to achieve the programming operation and a file system architecture based on the programming scheme to improve the efficiency of file management are also described.
    Type: Application
    Filed: April 30, 2009
    Publication date: December 22, 2011
    Inventors: Takashi Miida, Riichiro Shirota, Hideki Arakawa, Ching Sung Yang, Tzung Ling Lin
  • Publication number: 20100200260
    Abstract: A handheld tool includes a first power source, a second power source having a characteristic different from a characteristic of the first power source, and an operation part which is operated by a power from at least one of the first power source and the second power source to fasten a fastener.
    Type: Application
    Filed: September 11, 2007
    Publication date: August 12, 2010
    Applicant: MAX CO., LTD.
    Inventors: Mitsugu Mikami, Yoshiaki Adachi, Kouji Katou, Kigen Agehara, Takashi Miida
  • Publication number: 20100120193
    Abstract: An image sensor has a substrate, a dielectric layer positioned on the substrate, a pixel array including a plurality of pixels defined on the substrate, a shield electrode positioned between any two adjacent pixel electrodes of the pixels, a photo conductive layer positioned on the shield electrode and the pixel electrodes, and a transparent conductive layer covering the photo conductive layer.
    Type: Application
    Filed: January 21, 2010
    Publication date: May 13, 2010
    Inventor: Takashi Miida
  • Patent number: 7679157
    Abstract: An image sensor has a substrate, a dielectric layer positioned on the substrate, a pixel array including a plurality of pixels defined on the substrate, a shield electrode positioned between any two adjacent pixel electrodes of the pixels, a photo conductive layer positioned on the shield electrode and the pixel electrodes, and a transparent conductive layer covering the photo conductive layer.
    Type: Grant
    Filed: August 21, 2006
    Date of Patent: March 16, 2010
    Assignee: Powerchip Semiconductor Corp.
    Inventor: Takashi Miida
  • Publication number: 20080042230
    Abstract: An image sensor has a substrate, a dielectric layer positioned on the substrate, a pixel array including a plurality of pixels defined on the substrate, a shield electrode positioned between any two adjacent pixel electrodes of the pixels, a photo conductive layer positioned on the shield electrode and the pixel electrodes, and a transparent conductive layer covering the photo conductive layer.
    Type: Application
    Filed: August 21, 2006
    Publication date: February 21, 2008
    Inventor: Takashi Miida
  • Patent number: 7279384
    Abstract: A semiconductor memory has plural cell transistors that are arranged in a matrix. The cell transistor comprises a P type silicon substrate, a control gate CG and a pair of electrically isolated floating gates. Plural projections are formed in the silicon substrate, and a pair of N type diffusion regions as the source and the drain is formed in both sides of the projection. The control gate extending in the row direction faces the projection and the floating gate FG1, FG2 via an insulation layer. The width W1 of the floating gate FG1, FG2 in the column direction is larger than the width W2 of the control gate CG, so the floating gate FG1, FG2 and the control gate CG can be manufactured without the self-align process.
    Type: Grant
    Filed: November 22, 2005
    Date of Patent: October 9, 2007
    Assignee: Innotech Corporation
    Inventor: Takashi Miida
  • Patent number: 7256443
    Abstract: A semiconductor memory has plural cell transistors that are arranged in a matrix. The cell transistor comprises a silicon substrate, a control gate, a pair of electrically isolated floating gates. Plural projections are formed in the P type silicon substrate, and a pair of N type diffusion regions as the source and the drain is formed in both sides of the projection. The control gate faces the projection via a fourth insulation layer. The side surface of the floating gates faces the side surfaces of the projection via a first insulation layer, and faces the control gate via a third insulation layer. The floating gate faces the diffusion region via the first insulation layer.
    Type: Grant
    Filed: February 10, 2005
    Date of Patent: August 14, 2007
    Assignee: Innotech Corporation
    Inventor: Takashi Miida
  • Patent number: 7221029
    Abstract: A cell transistor includes source/drain regions formed at a lower level than part of its channel region. A select transistor has a channel region and source/drain regions formed at substantially the same level as the source/drain regions of the cell transistor. One of the source/drain regions of the cell transistor and one of the source/drain regions of the select transistor are electrically interconnected to each other in substantially the same plane.
    Type: Grant
    Filed: September 28, 2005
    Date of Patent: May 22, 2007
    Assignee: Innotech Corporation
    Inventor: Takashi Miida
  • Publication number: 20060108630
    Abstract: A semiconductor memory has plural cell transistors that are arranged in a matrix. The cell transistor comprises a P type silicon substrate, a control gate CG and a pair of electrically isolated floating gates. Plural projections are formed in the silicon substrate, and a pair of N type diffusion regions as the source and the drain is formed in both sides of the projection. The control gate extending in the row direction faces the projection and the floating gate FG1, FG2 via an insulation layer. The width W1 of the floating gate FG1, FG2 in the column direction is larger than the width W2 of the control gate CG, so the floating gate FG1, FG2 and the control gate CG can be manufactured without the self-align process.
    Type: Application
    Filed: November 22, 2005
    Publication date: May 25, 2006
    Inventor: Takashi Miida
  • Patent number: 7037782
    Abstract: A multiple-bit cell transistor includes a P type silicon substrate, a gate insulation layer, a pair of N type source/drain regions, a pair of tunnel insulation layers, and a pair of floating gates. The silicon substrate is formed with a projection while the floating gates each are positioned on one of opposite side walls of the projection. Inter-polycrystalline insulation layers each are formed on one of the floating gates. A control gate faces the top of the projection via the gate insulation layer. An N type region is formed on each side of the projection and contacts the source/drain region adjoining it. The cell transistor lowers a required write voltage, broadens a current window, and enhances resistance to inter-band tunneling.
    Type: Grant
    Filed: July 19, 2004
    Date of Patent: May 2, 2006
    Assignee: Innotech Corporation
    Inventor: Takashi Miida
  • Publication number: 20060027857
    Abstract: A cell transistor includes source/drain regions formed at a lower level than part of its channel region. A select transistor has a channel region and source/drain regions formed at substantially the same level as the source/drain regions of the cell transistor. One of the source/drain regions of the cell transistor and one of the source/drain regions of the select transistor are electrically interconnected to each other in substantially the same plane.
    Type: Application
    Filed: September 28, 2005
    Publication date: February 9, 2006
    Inventor: Takashi Miida
  • Patent number: 6984863
    Abstract: A cell transistor includes source/drain regions formed at a lower level than part of its channel region. A select transistor has a channel region and source/drain regions formed at substantially the same level as the source/drain regions of the cell transistor. One of the source/drain regions of the cell transistor and one of the source/drain regions of the select transistor are electrically interconnected to each other in substantially the same plane.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: January 10, 2006
    Assignee: Innotech Corporation
    Inventor: Takashi Miida
  • Patent number: 6950134
    Abstract: Disclosed is a method of storing optically generated charges by an optical signal in a solid state imaging device, which is particularly a method of storing optically generated charges by an optical signal in a solid state imaging device using a MOS image sensor of a threshold voltage modulation type, which is used for a video camera, an electronic camera, an image input camera, a scanner, a facsimile or the like.
    Type: Grant
    Filed: February 1, 2001
    Date of Patent: September 27, 2005
    Assignee: Innotech Corporation
    Inventor: Takashi Miida
  • Patent number: 6944062
    Abstract: A transistor includes p-type semiconductor (12) including a projection (13a) having a pair of side walls (13b, 13b) facing each other, a gate insulation layer (15c), a pair of n-type source/drain regions (BL1, BL2), tunnel insulation layers (15a), a pair of floating gates (FG1, FG2), inter-polycrystalline insulation layers, and a control gate (CG). The root portion of the projection (13A), which virtually connects the source/drain regions (BL1, BL2) with a straight line, is higher in the concentration of the p-type impurity than the other portion. A delete voltage for deleting charges stored in the floating gate (FG) is applied between the control gate (CG) and the source/drain region (BL1, BL2), so that a delete current flows toward the control gate (CG) or the source/drain region (BL1, BL2), the charges stored being deleted.
    Type: Grant
    Filed: April 26, 2004
    Date of Patent: September 13, 2005
    Assignee: Innotech Corporation
    Inventor: Takashi Miida
  • Publication number: 20050190605
    Abstract: A semiconductor memory has plural cell transistors that are arranged in a matrix. The cell transistor comprises a silicon substrate, a control gate, a pair of electrically isolated floating gates. Plural projections are formed in the P type silicon substrate, and a pair of N type diffusion regions as the source and the drain is formed in both sides of the projection. The control gate faces the projection via a fourth insulation layer. The side surface of the floating gates faces the side surfaces of the projection via a first insulation layer, and faces the control gate via a third insulation layer. The floating gate faces the diffusion region via the first insulation layer.
    Type: Application
    Filed: February 10, 2005
    Publication date: September 1, 2005
    Inventor: Takashi Miida
  • Patent number: 6937525
    Abstract: A multiple-bit transistor includes P type semiconductor including a projection, a gate insulation layer, a pair of N type source/drain regions, tunnel insulation layers, a pair of floating gates, inter-polycrystalline insulation layers, and a control gate. The root portion of the projection, which is defined by a straight line virtually connecting the source/drain regions, is higher in the concentration of the P type impurity than the other portion. A potential difference for write-in is set up between the source/drain regions while a write voltage is applied to the control gate, thereby causing electrons to be ballistically injected into at least one of the floating gates.
    Type: Grant
    Filed: November 20, 2002
    Date of Patent: August 30, 2005
    Assignee: Innotech Corporation
    Inventor: Takashi Miida