Abstract: A multiple-bit transistor includes P type semiconductor including a projection, a gate insulation layer, a pair of N type source/drain regions, tunnel insulation layers, a pair of floating gates, inter-polycrystalline insulation layers, and a control gate. The root portion of the projection, which is defined by a straight line virtually connecting the source/drain regions, is higher in the concentration of the P type impurity than the other portion. A potential difference for write-in is set up between the source/drain regions while a write voltage is applied to the control gate, thereby causing electrons to be ballistically injected into at least one of the floating gates.

Abstract: A multiple-bit cell transistor includes a P type silicon substrate, agate insulation layer, a pair of N type source/drain regions, a pair of tunnel insulation layers, and a pair of floating gates. The silicon substrate is formed with a projection while the floating gates each are positioned on one of opposite side walls of the projection. Inter-polycrystalline insulation layers each are formed on one of the floating gates. A control gate faces the top of the projection via the gate insulation layer. An N type region is formed on each side of the projection and contacts the source/drain region adjoining it. The cell transistor lowers a required write voltage, broadens a current window, and enhances resistance to inter-band tunneling.

Abstract: A multiple-bit cell transistor includes a P type silicon substrate, agate insulation layer, a pair of N type source/drain regions, a pair of tunnel insulation layers, and a pair of floating gates. The silicon substrate is formed with a projection while the floating gates each are positioned on one of opposite side walls of the projection. Inter-polycrystalline insulation layers each are formed on one of the floating gates. A control gate faces the top of the projection via the gate insulation layer. An N type region is formed on each side of the projection and contacts the source/drain region adjoining it. The cell transistor lowers a required write voltage, broadens a current window, and enhances resistance to inter-band tunneling.

Abstract: A transistor includes p-type semiconductor (12) including a projection (13a) having a pair of side walls (13b, 13b) facing each other, a gate insulation layer (15c), a pair of n-type source/drain regions (BL1, BL2), tunnel insulation layers (15a), a pair of floating gates (FG1, FG2), inter-polycrystalline insulation layers, and a control gate (CG). The root portion of the projection (13A), which virtually connects the source/drain regions (BL1, BL2) with a straight line, is higher in the concentration of the p-type impurity than the other portion. A delete voltage for deleting charges stored in the floating gate (FG) is applied between the control gate (CG) and the source/drain region (BL1, BL2), so that a delete current flows toward the control gate (CG) or the source/drain region (BL1, BL2), the charges stored being deleted.

Abstract: A flash memory includes a pair of floating gates formed on opposite side walls of a projection and each facing one side wall and one source/drain region via a tunnel insulation layer. The floating gates each have a substantially square cross-section in a direction perpendicular to the direction of column. The square cross-section faces one of the side wall of the projection via the tunnel insulation layer at one of two continuous sides, faces the source/drain region via the tunnel insulation layer at the other side, and faces a control gate via an inter-polycrystalline insulation layer at another side.

Abstract: Disclosed is a solid state imaging device, comprising a unit pixel 101 including a photo diode 111 and a MOS transistor 112 for optical signal detection provided with a high-density buried layer 25 for storing optically generated charges generated by light irradiation in the photo diode 111, a vertical scanning signal driving scanning circuit 102 for outputting a scanning signal to a gate electrode 19, and a voltage boost scanning circuit 108 for outputting a boosted voltage higher than a power source voltage to a source region 16. In this case, a boosted voltage is applied from the voltage boost scanning circuit 108 to the source region 16, and the optically generated charges stored in the high-density buried layer 25 are swept out from the high-density buried layer 25 by a source voltage and a gate voltage risen by the boosted voltage.

Abstract: A solid-state imaging device is provided, which is capable of increasing an S/N ratio while enhancing a dynamic range, when a photoelectric signal is converted into a digital signal. This solid-state imaging device comprises: a plurality of photoelectric conversion devices arrayed in rows and columns, each of the photoelectric conversion devices converting an optical signal into an electric signal and outputting a first signal voltage; a difference signal generation circuit provided for each column, for sequentially inputting the first signal voltage and a second signal voltage obtained by initializing the photoelectric conversion devices, thereafter converting the first signal voltage and the second signal voltage into charges, generating a difference signal therebetween, and then outputting the difference signal after adjusting a gain according to a level of the difference signal; and an analog/digital conversion circuit connected to the output of the difference signal generation circuit.

Abstract: A solid state imaging device includes a MOS image sensor of a threshold voltage modulation system employed in a video camera, an electronic camera, an image input camera, a scanner, a facsimile, or the like. The solid state imaging device includes a photo diode formed in a second semiconductor layer of opposite conductivity type in a first semiconductor layer of one conductivity type, and a light signal detecting insulated gate field effect transistor formed in a fourth semiconductor layer of the opposite conductivity type in a third semiconductor layer of one conductivity type adjacent to the photo diode. A carrier pocket is provided in the fourth semiconductor layer and a portion of the first semiconductor layer under the second semiconductor layer is thicker than that portion of the third semiconductor layer under the fourth semiconductor layer.

Abstract: A first buried layer of one conductivity and a first well region of opposite conductivity are formed in a semiconductor layer using a first mask. A second mask is used to form a second buried layer and a second well region of the opposite conductivity and to introduce impurity of the one conductivity type into a surface of the second well to form a channel doped layer of the one conductivity. A high concentration buried layer of the opposite conductivity is formed by introducing opposite conductivity impurity into the second well region using a third mask. A gate insulating film is formed on the semiconductor layer by thermal oxidation. A source region and a drain region of the one conductivity type are formed on the surface of the second well region, on both sides of a gate electrode.

Abstract: A sole state imaging device includes a photodetection diode and an insulated gate field effect transistor provided adjacent to the photodetection diode for optical signal detection. In a method of making the device, a carrier pocket is formed in a second well region, and an element isolation insulating film is formed to isolate adjacent unit pixels from each other. In addition, an element isolation region of an opposite conductivity type is formed to isolate a second semiconductor layer of one conductivity type in such a way as to include the lower surface of the element isolation insulating film and reach a first semiconductor layer.

Abstract: A cell transistor includes source/drain regions formed at a lower level than part of its channel region. A select transistor has a channel region and source/drain regions formed at substantially the same level as the source/drain regions of the cell transistor. One of the source/drain regions of the cell transistor and one of the source/drain regions of the select transistor are electrically interconnected to each other in substantially the same plane.

Abstract: A multiple-bit transistor includes P type semiconductor including a projection, a gate insulation layer, a pair of N type source/drain regions, tunnel insulation layers, a pair of floating gates, inter-polycrystalline insulation layers, and a control gate. The root portion of the projection, which is defined by a straight line virtually connecting the source/drain regions, is higher in the concentration of the P type impurity than the other portion. A potential difference for write-in is set up between the source/drain regions while a write voltage is applied to the control gate, thereby causing electrons to be ballistically injected into at least one of the floating gates.

Abstract: A multiple-bit cell transistor includes a P type silicon substrate, agate insulation layer, a pair of N type source/drain regions, a pair of tunnel insulation layers, and a pair of floating gates. The silicon substrate is formed with a projection while the floating gates each are positioned on one of opposite side walls of the projection. Inter-polycrystalline insulation layers each are formed on one of the floating gates. A control gate faces the top of the projection via the gate insulation layer. An N type region is formed on each side of the projection and contacts the source/drain region adjoining it. The cell transistor lowers a required write voltage, broadens a current window, and enhances resistance to inter-band tunneling.

Abstract: Disclosed is a solid state imaging device, comprising: a photodetection diode; and an insulated gate field effect transistor provided adjacent to the photodetection diode for optical signal detection. In this case, a carrier pocket is provided in a second well region, and an element isolation insulating film is formed to isolate adjacent unit pixels from each other. In addition, an element isolation region of an opposite conductivity type is formed to isolate a second semiconductor layer of one conductivity type in such a way as to include the lower surface of the element isolation insulating film and reach a first semiconductor layer.

Abstract: Disclosed is a solid state imaging device, comprising: a photodetection diode; and an insulated gate field effect transistor provided adjacent to the photodetection diode for optical signal detection. In this case, a carrier pocket is provided in a second well region, and an element isolation insulating film is formed to isolate adjacent unit pixels from each other. In addition, an element isolation region of an opposite conductivity type is formed to isolate a second semiconductor layer of one conductivity type in such a way as to include the lower surface of the element isolation insulating film and reach a first semiconductor layer.

Abstract: The present invention relates to a dual bit nonvolatile programmable read/write memory containing a semiconductor memory element having one conductivity type semiconductor substrate including at least one convex portion. A pair of opposite conductivity source/drain regions are formed on a surface of the semiconductor substrate an opposing sides of the convex portion, and a first insulating film covers the upper surface of the convex portion. Second insulating films cover the side surfaces of the convex portion and the source/drain regions. A pair of floating gates abut opposing side surfaces of the convex portion and the source/drain regions through the second insulating films. Third insulating films are formed on the floating gates. A control gate covers the upper surface of the convex portion through the first insulating film and the floating gates through the third insulating films.

Abstract: The present invention is a method for detecting photo signals using an imaging device, comprising steps of photo-generating holes in a well region 15 of a photo-diode by a signal light, transferring the photo-generated holes through a bulk of the well region 15 to a heavily doped buried layer 25 which is formed in the well region 15 near a source region 16 by doping that region with impurity heavier than the well region (15) of an insulated gate FET, storing the photo-generated holes in the heavily doped buried layer 25 to thereby change the threshold of the FET corresponding to the amount of the photo-generated charge, and reading the change in the threshold as the amount of signal light received by the photo-sensor.

Abstract: Disclosed is a solid state imaging device, comprising a unit pixel 101 including a photo diode 111 and a MOS transistor 112 for optical signal detection provided with a high-density buried layer 25 for storing optically generated charges generated by light irradiation in the photo diode 111, a vertical scanning signal driving scanning circuit 102 for outputting a scanning signal to a gate electrode 19, and a voltage boost scanning circuit 108 for outputting a boosted voltage higher than a power source voltage to a source region 16. In this case, a boosted voltage is applied from the voltage boost scanning circuit 108 to the source region 16, and the optically generated charges stored in the high-density buried layer 25 are swept out from the high-density buried layer 25 by a source voltage and a gate voltage risen by the boosted voltage.

Abstract: There is provided a solid state imaging device using a MOS image sensor of a threshold voltage modulation system employed in a video camera, an electronic camera, an image input camera, a scanner, a facsimile, or the like. In configuration, in the solid state imaging device that comprises a photo diode formed in a second semiconductor layer 15a of opposite conductivity type in a first semiconductor layer 12 and 32 of one conductivity type, and a light signal detecting insulated gate field effect transistor formed in a fourth semiconductor layer 15b of opposite conductivity type in a third semiconductor layer 12 of one conductivity type adjacently to the photo diode, a carrier pocket 25 is provided in the fourth semiconductor layer 15b, and a portion of the first semiconductor layer 12, 32 under the second semiconductor layer 15a is thicker than a portion of the third semiconductor layer 12 under the fourth semiconductor layer 15b in a depth direction.

Abstract: There is provided a solid state imaging device using a MOS image sensor of a threshold voltage modulation system employed in a video camera, an electronic camera, an image input camera, a scanner, a facsimile, or the like. In configuration, in the solid state imaging device that comprises a photo diode formed in a second semiconductor layer 15a of opposite conductivity type in a first semiconductor layer 12 and 32 of one conductivity type, and a light signal detecting insulated gate field effect transistor formed in a fourth semiconductor layer 15b of opposite conductivity type in a third semiconductor layer 12 of one conductivity type adjacently to the photo diode, a carrier pocket 25 is provided in the fourth semiconductor layer 15b, and a portion of the first semiconductor layer 12, 32 under the second semiconductor layer 15a is thicker than a portion of the third semiconductor layer 12 under the fourth semiconductor layer 15b in a depth direction.