Patents by Inventor Takashi Noma
Takashi Noma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20220384204Abstract: Implementations of a semiconductor package may include a die; a first pad and a second pad, the first pad and the second pad each including a first layer and a second layer where the second layer may be thicker than the first layer. At least a first conductor may be directly coupled to the second layer of the first pad; at least a second conductor may be directly coupled to the second layer of the second pad; and an organic material may cover at least the first side of the die. The at least first conductor and the at least second conductor extend through openings in the organic material where a spacing between the at least first conductor and the at least second conductor may be wider than a spacing between the second layer of the first pad and the second layer of the second pad.Type: ApplicationFiled: June 23, 2022Publication date: December 1, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Francis J. CARNEY, Michael J. SEDDON, Yusheng LIN, Takashi NOMA, Eiji KUROSE
-
Patent number: 11508579Abstract: Implementations of die singulation systems and related methods may include forming a plurality of die on a first side of a substrate, forming a backside metal layer on a second side of a substrate, applying a photoresist layer over the backside metal layer, patterning the photoresist layer along a die street of the substrate, and forming a groove at the pattern of the photoresist layer only partially through a thickness of the backside metal layer. The groove may be located in the die street of the substrate. The method may also include etching through a remaining portion of the backside metal layer located in the die street, removing the photoresist layer, and singulating the plurality of die included in the substrate by removing substrate material in the die street.Type: GrantFiled: December 28, 2020Date of Patent: November 22, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Takashi Noma, Michael J. Seddon
-
Publication number: 20220359360Abstract: A system-in-package includes an interposer substrate having a first side and a second side opposite the first side, and a redistribution layer disposed on the first side. The redistribution layer includes a plurality of contact pads and a plurality of interconnections disposed on the first side. The plurality of interconnections is electrically connected to a plurality of terminals disposed on the second side opposite the first side. A first semiconductor die is disposed on the first side and electrically coupled to a first of the plurality of contact pads and a first of the plurality of interconnections disposed on the first side of the interposer substrate. A second semiconductor die is disposed on the first side. The second semiconductor die is electrically coupled to a second of the plurality of contact pads and a second of the plurality of interconnections disposed on the first side of the interposer substrate.Type: ApplicationFiled: April 29, 2022Publication date: November 10, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yusheng LIN, Takashi NOMA
-
Publication number: 20220319894Abstract: Implementations of a method of making a plurality of alignment marks on a wafer may include: providing a wafer including an alignment feature on a first side of the wafer. The method may include aligning the wafer using a camera focused on the first side of the wafer. The wafer may be aligned using the alignment feature on the first side of the die. The wafer may also include creating a plurality of alignment marks on a second side of the wafer through lasering, sawing, or scribing.Type: ApplicationFiled: June 24, 2022Publication date: October 6, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Michael J. SEDDON, Takashi NOMA
-
Patent number: 11446608Abstract: The present invention relates to a method for reducing the HTO concentration in a tritium-containing aqueous solution. The present invention includes bringing water vapor or the like of a tritium-containing aqueous solution into contact with a porous material having pores in a pore diameter range of 500 ? or less, selectively occluding the HTO in the tritium-containing aqueous solution in the porous material, and obtaining a tritium-containing aqueous solution in which the HTO concentration thereof is reduced. The present invention relates to a device used for reducing the HTO concentration in a tritium-containing aqueous solution.Type: GrantFiled: May 29, 2018Date of Patent: September 20, 2022Assignees: KINKI UNIVERSITY, A ATOM TECHNOL KINDAI, TOYO ALUMINIUM KABUSHIKI KAISHAInventors: Tatsuhiko Ihara, Hirokuni Yamanishi, Hiroshi Noma, Toshifumi Taira, Takashi Hoshiya, Kazuya Fujimoto
-
Publication number: 20220285267Abstract: In a general aspect, a semiconductor device assembly can include a semiconductor die having a back side and a front side, the back side being coupled with a base, the front side including active circuitry. The assembly can include a first resin encapsulation layer disposed on a first portion of the front side. The first resin encapsulation layer can be patterned to define a first opening exposing a second portion of the front side through the first resin encapsulation layer. The assembly can include a signal distribution structure that is disposed on the first resin encapsulation layer, and electrically coupled with the front side through the first opening. The assembly can include a second resin encapsulation layer disposed on a first portion of the signal distribution structure, the second resin encapsulation layer being patterned to define a second opening that exposes a second portion of the signal distribution structure.Type: ApplicationFiled: March 2, 2021Publication date: September 8, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Takashi NOMA, Yusheng LIN
-
Publication number: 20220270884Abstract: Implementations of a semiconductor package may include a semiconductor die including a first side and a second side, the first side of the semiconductor die including one or more electrical contacts; and an organic material covering at least the first side of the semiconductor die. Implementations may include where the one or more electrical contacts extend through one or more openings in the organic material; a metal-containing layer coupled to the one or more electrical contacts; and one or more slugs coupled to one of a first side of the semiconductor die, a second side of the semiconductor die, or both the first side of the semiconductor die and the second side of the semiconductor die.Type: ApplicationFiled: May 10, 2022Publication date: August 25, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yusheng LIN, Michael J. SEDDON, Francis J. CARNEY, Takashi NOMA, Eiji KUROSE
-
Patent number: 11393692Abstract: Implementations of a semiconductor package may include a die; a first pad and a second pad, the first pad and the second pad each including a first layer and a second layer where the second layer may be thicker than the first layer. At least a first conductor may be directly coupled to the second layer of the first pad; at least a second conductor may be directly coupled to the second layer of the second pad; and an organic material may cover at least the first side of the die. The at least first conductor and the at least second conductor extend through openings in the organic material where a spacing between the at least first conductor and the at least second conductor may be wider than a spacing between the second layer of the first pad and the second layer of the second pad.Type: GrantFiled: April 29, 2020Date of Patent: July 19, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Francis J. Carney, Michael J. Seddon, Yusheng Lin, Takashi Noma, Eiji Kurose
-
Patent number: 11387130Abstract: Implementations of a method of making a plurality of alignment marks on a wafer may include: providing a wafer including an alignment feature on a first side of the wafer. The method may include aligning the wafer using a camera focused on the first side of the wafer. The wafer may be aligned using the alignment feature on the first side of the die. The wafer may also include creating a plurality of alignment marks on a second side of the wafer through lasering, sawing, or scribing.Type: GrantFiled: July 9, 2019Date of Patent: July 12, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Michael J. Seddon, Takashi Noma
-
Patent number: 11367619Abstract: Implementations of a semiconductor package may include a semiconductor die including a first side and a second side, the first side of the semiconductor die including one or more electrical contacts; and an organic material covering at least the first side of the semiconductor die. Implementations may include where the one or more electrical contacts extend through one or more openings in the organic material; a metal-containing layer coupled to the one or more electrical contacts; and one or more slugs coupled to one of a first side of the semiconductor die, a second side of the semiconductor die, or both the first side of the semiconductor die and the second side of the semiconductor die.Type: GrantFiled: April 29, 2020Date of Patent: June 21, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yusheng Lin, Michael J. Seddon, Francis J. Carney, Takashi Noma, Eiji Kurose
-
Publication number: 20220181192Abstract: At least one circuit element may be formed on a front side of a ringed substrate, and the ringed substrate may be mounted on a mounting chuck. The mounting chuck may have an inner raised portion configured to receive the thinned portion of the substrate thereon, and a recessed ring around a perimeter of the mounting chuck configured to receive the outer ring of the ringed substrate therein. At least one solder bump may be formed that is electrically connected to the at least one circuit element, while the ringed wafer is disposed on the mounting chuck.Type: ApplicationFiled: February 28, 2022Publication date: June 9, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Takashi NOMA, Noboru OKUBO, Yusheng LIN
-
Publication number: 20220172994Abstract: Implementations of a method for aligning a semiconductor wafer for singulation may include: providing a semiconductor wafer having a first side and a second side. The first side of the wafer may include a plurality of die and the plurality of die may be separated by streets. The semiconductor wafer may include an edge ring around a perimeter of the wafer on the second side of the wafer. The wafer may also include a metal layer on the second side of the wafer. The metal layer may substantially cover the edge ring. The method may include grinding the edge ring to create an edge exclusion area and aligning the semiconductor wafer with a saw using a camera positioned in the edge exclusion area on the second side of the wafer. Aligning the wafer may include using three or more alignment features included in the edge exclusion area.Type: ApplicationFiled: February 18, 2022Publication date: June 2, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Michael J. SEDDON, Takashi NOMA
-
Publication number: 20220131002Abstract: According to an aspect, a semiconductor device for integrating multiple transistors includes a wafer substrate including a first region and a second region. The first region defines at least a portion of at least one first transistor. The second region defines at least a portion of at least one second transistor. The semiconductor device includes an isolation area located between the first region and the second region, at least one terminal of the at least one first transistor contacting the first region of the wafer substrate, at least one terminal of the at least one second transistor contacting the second region of the wafer substrate, and an encapsulation material, where the encapsulation material includes a portion located within the isolation area.Type: ApplicationFiled: October 26, 2020Publication date: April 28, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Takashi NOMA, Yusheng LIN, Kazuo OKADA, Hideaki YOSHIMI, Shunsuke YASUDA
-
Patent number: 11289381Abstract: Implementations of a method for aligning a semiconductor wafer for singulation may include: providing a semiconductor wafer having a first side and a second side. The first side of the wafer may include a plurality of die and the plurality of die may be separated by streets. The semiconductor wafer may include an edge ring around a perimeter of the wafer on the second side of the wafer. The wafer may also include a metal layer on the second side of the wafer. The metal layer may substantially cover the edge ring. The method may include grinding the edge ring to create an edge exclusion area and aligning the semiconductor wafer with a saw using a camera positioned in the edge exclusion area on the second side of the wafer. Aligning the wafer may include using three or more alignment features included in the edge exclusion area.Type: GrantFiled: October 12, 2020Date of Patent: March 29, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Michael J. Seddon, Takashi Noma
-
Patent number: 11264264Abstract: At least one circuit element may be formed on a front side of a ringed substrate, and the ringed substrate may be mounted on a mounting chuck. The mounting chuck may have an inner raised portion configured to receive the thinned portion of the substrate thereon, and a recessed ring around a perimeter of the mounting chuck configured to receive the outer ring of the ringed substrate therein. At least one solder bump may be formed that is electrically connected to the at least one circuit element, while the ringed wafer is disposed on the mounting chuck.Type: GrantFiled: October 23, 2019Date of Patent: March 1, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Takashi Noma, Noboru Okubo, Yusheng Lin
-
Patent number: 11257759Abstract: According to an aspect, a semiconductor device for integrating multiple transistors includes a wafer substrate including a first region and a second region, where the first region defines at least a portion of at least one first transistor and the second region defines at least a portion of at least one second transistor. The semiconductor device includes an isolation area located between the first region and the second region, at least one conductive pad of the at least one first transistor contacting the first region of the wafer substrate, at least one conductive pad of the at least one second transistor contacting the second region of the wafer substrate, a backplate coupled to the wafer substrate, and an encapsulation material, where the encapsulation material has a portion contacting the backplate, and the encapsulation material includes a portion located within the isolation area.Type: GrantFiled: October 26, 2020Date of Patent: February 22, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Francis J. Carney, Yusheng Lin, Takashi Noma
-
Publication number: 20220028812Abstract: A semiconductor wafer has an edge support ring around a perimeter of the semiconductor wafer and conductive layer formed over a surface of the semiconductor wafer within the edge support ring. A first stencil is disposed over the edge support ring with first openings aligned with the conductive layer. The first stencil includes a horizontal portion over the edge support ring, and a step-down portion extending the first openings to the conductive layer formed over the surface of the semiconductor wafer. The horizontal portion may have a notch with the edge support ring disposed within the notch. A plurality of bumps is dispersed over the first stencil to occupy the first openings over the conductive layer. A second stencil is disposed over the edge support ring with second openings aligned with the conductive layer to deposit a flux material in the second openings over the conductive layer.Type: ApplicationFiled: October 5, 2021Publication date: January 27, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Michael J. SEDDON, Takashi NOMA, Kazuhiro SAITO
-
Patent number: 11164835Abstract: A semiconductor wafer has an edge support ring around a perimeter of the semiconductor wafer and conductive layer formed over a surface of the semiconductor wafer within the edge support ring. A first stencil is disposed over the edge support ring with first openings aligned with the conductive layer. The first stencil includes a horizontal portion over the edge support ring, and a step-down portion extending the first openings to the conductive layer formed over the surface of the semiconductor wafer. The horizontal portion may have a notch with the edge support ring disposed within the notch. A plurality of bumps is dispersed over the first stencil to occupy the first openings over the conductive layer. A second stencil is disposed over the edge support ring with second openings aligned with the conductive layer to deposit a flux material in the second openings over the conductive layer.Type: GrantFiled: January 15, 2018Date of Patent: November 2, 2021Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Michael J. Seddon, Takashi Noma, Kazuhiro Saito
-
Publication number: 20210305096Abstract: In a general aspect, a fan-out wafer level package (FOWLP) can include a semiconductor die having an active surface, a backside surface, a plurality of side surfaces, each side surface of the plurality of side surfaces extending between the active surface and the backside surface, a plurality of conductive bumps disposed on the active surface, and an insulating layer disposed on a first portion of the active surface between the conductive bumps. The FOWLP can also include a molding compound encapsulating the backside surface, the plurality of side surfaces, and a second portion of the active surface between the conductive bumps and a perimeter edge of the active surface. The FOWLP can also include a signal distribution structure disposed on the conductive bumps, the insulating layer and the molding compound. The signal distribution structure can be configured to provide respective electrical connections to the plurality of conductive bumps.Type: ApplicationFiled: June 15, 2021Publication date: September 30, 2021Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: George CHANG, Yusheng LIN, Gordon M. GRIVNA, Takashi NOMA
-
Patent number: 11114402Abstract: Implementations of semiconductor devices may include a die having a first side and a second side, a contact pad coupled to the first side of the die, and a metal layer coupled to the second side of the die. A thickness of the die may be no more than four times a thickness of the metal layer.Type: GrantFiled: February 23, 2018Date of Patent: September 7, 2021Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Michael J. Seddon, Takashi Noma, Kazuo Okada, Hideaki Yoshimi, Naoyuki Yomoda, Yusheng Lin