Abstract: Implementations of semiconductor packages may include a die having a first side and a second side opposite the first side, a first metal layer coupled to the first side of the die, a tin layer coupled to the first metal layer, the first metal layer between the die and the tin layer, a backside metal layer coupled to the second side of the die, and a mold compound coupled to the die. The mold compound may cover a plurality of sidewalls of the first metal layer and a plurality of sidewalls of the tin layer and a surface of the mold compound is coplanar with a surface of the tin layer.

Abstract: Implementations of a semiconductor package may include a semiconductor die including a first side and a second side, the first side of the semiconductor die including one or more electrical contacts; and an organic material covering at least the first side of the semiconductor die. Implementations may include where the one or more electrical contacts extend through one or more openings in the organic material; a metal-containing layer coupled to the one or more electrical contacts; and one or more slugs coupled to one of a first side of the semiconductor die, a second side of the semiconductor die, or both the first side of the semiconductor die and the second side of the semiconductor die.

Abstract: Implementations of a method of making a plurality of alignment marks on a wafer may include: providing a wafer including an alignment feature on a first side of the wafer. The method may include aligning the wafer using a camera focused on the first side of the wafer. The wafer may be aligned using the alignment feature on the first side of the die. The wafer may also include creating a plurality of alignment marks on a second side of the wafer through lasering, sawing, or scribing.

Abstract: Implementations of a method for wafer alignment may include: providing a wafer having a first side and a second side and forming a seed layer on a second side of the wafer. The method may include applying a glop to the seed layer at two or more predetermined points and plating a metal layer over the seed layer and around the glop. The method may include removing the glop to expose the seed layer and etching the seed layer to expose a plurality of alignment features on the second side of the wafer.

Abstract: Implementations of die singulation systems and related methods may include forming a plurality of die on a first side of a substrate, forming a backside metal layer on a second side of a substrate, applying a photoresist layer over the backside metal layer, patterning the photoresist layer along a die street of the substrate, and forming a groove at the pattern of the photoresist layer only partially through a thickness of the backside metal layer. The groove may be located in the die street of the substrate. The method may also include etching through a remaining portion of the backside metal layer located in the die street, removing the photoresist layer, and singulating the plurality of die included in the substrate by removing substrate material in the die street.

Abstract: Implementations of a method for aligning a semiconductor wafer for singulation may include: providing a semiconductor wafer having a first side and a second side. The first side of the wafer may include a plurality of die and the plurality of die may be separated by streets. The semiconductor wafer may include an edge ring around a perimeter of the wafer on the second side of the wafer. The wafer may also include a metal layer on the second side of the wafer. The metal layer may substantially cover the edge ring. The method may include grinding the edge ring to create an edge exclusion area and aligning the semiconductor wafer with a saw using a camera positioned in the edge exclusion area on the second side of the wafer. Aligning the wafer may include using three or more alignment features included in the edge exclusion area.

Abstract: An ESD protection device includes first and second discharge electrodes and a discharge auxiliary electrode that is electrically connected to the first and second discharge electrodes. The first and second discharge electrodes are located on or in an insulating substrate to at least partially face each other. The discharge auxiliary electrode includes first metal particles, second metal particles, and a binding agent. The first metal particles have a core-shell structure including a core section mainly including a first metal and a shell section which mainly includes an oxide of a second metal and which includes at least one portion with a cavity. The second metal particles have a core-shell structure including a core section mainly including the first metal and a shell section which mainly includes the oxide of the second metal and which has no cavity.

Abstract: A method for making an integrated passive device (IPD) die includes grinding a backside of a semiconductor substrate to reduce a thickness of a central portion of the semiconductor substrate while leaving a mechanical support ring on an outer portion of the substrate, and forming a through-substrate via (TSV) from the backside of the substrate. The TSV defines interconnect access to at least one passive component embedded in an insulator material disposed on a front surface of the semiconductor substrate. The substrate has a thickness less than three-quarters of an original thickness of the substrate.

Abstract: In a general aspect, a fan-out wafer level package (FOWLP) can include a semiconductor die having an active surface, a backside surface, a plurality of side surfaces, each side surface of the plurality of side surfaces extending between the active surface and the backside surface, a plurality of conductive bumps disposed on the active surface, and an insulating layer disposed on a first portion of the active surface between the conductive bumps. The FOWLP can also include a molding compound encapsulating the backside surface, the plurality of side surfaces, and a second portion of the active surface between the conductive bumps and a perimeter edge of the active surface. The FOWLP can also include a signal distribution structure disposed on the conductive bumps, the insulating layer and the molding compound. The signal distribution structure can be configured to provide respective electrical connections to the plurality of conductive bumps.

Abstract: A method of forming semiconductor devices includes providing a wafer having a first side and second side, electrically conductive pads at the second side, and an electrically insulative layer at the second side with openings to the pads. The first side of the wafer is background to a desired thickness and an electrically conductive layer is deposited thereon. Nickel layers are simultaneously electrolessly deposited over the electrically conductive layer and over the pads, and diffusion barrier layers are then simultaneously deposited over the nickel layers. Another method of forming semiconductor devices includes depositing backmetal (BM) layers on the electrically conductive layer including a titanium layer, a nickel layer, and/or a silver layer. The BM layers are covered with a protective coating and a nickel layer is electrolessly deposited over the pads. A diffusion barrier layer is deposited over the nickel layer over the pads, and the protective coating is removed.

Abstract: In one general aspect, an integrated passive device (IPD) die includes at least one passive component that is embedded in an insulator material disposed on a front surface of a substrate. The IPD die includes a through-substrate via (TSV) extending from the backside of the substrate toward the front surface of the substrate. The TSV defines interconnect access to at least one passive component embedded in the insulator material disposed on the front surface of the substrate. The substrate has a thickness less than three-quarters of an original thickness of the substrate.

Abstract: An interposer substrate includes a body, first to third external connection conductors, and a wiring conductor. The body includes first to third principal surfaces. A distance between the first and second principal surfaces is different from a distance between the first and third principal surfaces. The first external connection conductor is provided on the first principal surface and is connected to an external circuit board. The second external connection conductor is provided on the second principal surface and is connected to a first flat cable. The third external connection conductor is provided on the third principal surface and is connected to a second flat cable. The wiring conductor is provided in the body, and connects the first external connection conductor and second and third external connection conductors.

Abstract: Implementations of semiconductor packages may include a die having a first side and a second side opposite the first side, a first metal layer coupled to the first side of the die, a tin layer coupled to the first metal layer, the first metal layer between the die and the tin layer, a backside metal layer coupled to the second side of the die, and a mold compound coupled to the die. The mold compound may cover a plurality of sidewalls of the first metal layer and a plurality of sidewalls of the tin layer and a surface of the mold compound is coplanar with a surface of the tin layer.

Abstract: Implementations of semiconductor devices may include a die having a first side and a second side, a contact pad coupled to the first side of the die, and a metal layer coupled to the second side of the die. A thickness of the die may be no more than four times a thickness of the metal layer.

Abstract: Implementations of a semiconductor device may include: a silicon substrate including a first side and a second side. The second side of the substrate may include an active area. The device may include a metal stack including: a back metallization on the first side of the substrate, an electroplated metal layer on the back metallization; and an evaporated gold metal layer on the electroplated metal layer.

Abstract: In one general aspect, an integrated passive device (IPD) die includes at least one passive component that is embedded in an insulator material disposed on a front surface of a substrate. The IPD die includes a through-substrate via (TSV) extending from the backside of the substrate toward the front surface of the substrate. The TSV defines interconnect access to at least one passive component embedded in the insulator material disposed on the front surface of the substrate. The substrate has a thickness less than three-quarters of an original thickness of the substrate.

Abstract: A power supply module includes a substrate, a switching control IC and a coil. The coil includes a plurality of metal posts, first ends of which are mounted on a first surface of the substrate, wiring conductors that are in conductive contact with the first ends of the metal posts, and post connection conductors that are in conductive contact with second ends of the metal posts. The power supply module further includes a magnetic core that strengthens magnetic flux generated by the coil, and a sealing resin that seals the metal posts and the magnetic core.

Abstract: An ESD protection device includes first and second discharge electrodes and a discharge auxiliary electrode that is electrically connected to the first and second discharge electrodes. The first and second discharge electrodes are located on or in an insulating substrate to at least partially face each other. The discharge auxiliary electrode includes first metal particles, second metal particles, and a binding agent. The first metal particles have a core-shell structure including a core section mainly including a first metal and a shell section which mainly includes an oxide of a second metal and which includes at least one portion with a cavity. The second metal particles have a core-shell structure including a core section mainly including the first metal and a shell section which mainly includes the oxide of the second metal and which has no cavity.

Abstract: To ensure a sufficient communication distance and to concurrently suppress a conductor loss, a coil antenna includes a magnetic core including a first peripheral surface including at least a first principal surface, a first coil conductor located on the first principal surface and wound around a predetermined winding axis, a first base material layer stacked on the first principal surface, including at least a first surface parallel or substantially parallel to the first principal surface, and made of a material having a lower magnetic permeability than the magnetic core, and a second coil conductor located on at least the first surface. Opposite ends of the second coil conductor are coupled to the first coil conductor on the first principal surface, and a direction in which a current flows through the first coil conductor on the first principal surface is substantially the same as a direction in which a current flows through the second coil conductor on the first surface.

Abstract: A semiconductor wafer has an edge support ring around a perimeter of the semiconductor wafer and conductive layer formed over a surface of the semiconductor wafer within the edge support ring. A first stencil is disposed over the edge support ring with first openings aligned with the conductive layer. The first stencil includes a horizontal portion over the edge support ring, and a step-down portion extending the first openings to the conductive layer formed over the surface of the semiconductor wafer. The horizontal portion may have a notch with the edge support ring disposed within the notch. A plurality of bumps is dispersed over the first stencil to occupy the first openings over the conductive layer. A second stencil is disposed over the edge support ring with second openings aligned with the conductive layer to deposit a flux material in the second openings over the conductive layer.