Patents by Inventor Takashi Noma

Takashi Noma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9905525
    Abstract: A semiconductor wafer has an edge support ring around a perimeter of the semiconductor wafer and conductive layer formed over a surface of the semiconductor wafer within the edge support ring. A first stencil is disposed over the edge support ring with first openings aligned with the conductive layer. The first stencil includes a horizontal portion over the edge support ring, and a step-down portion extending the first openings to the conductive layer formed over the surface of the semiconductor wafer. The horizontal portion may have a notch with the edge support ring disposed within the notch. A plurality of bumps is dispersed over the first stencil to occupy the first openings over the conductive layer. A second stencil is disposed over the edge support ring with second openings aligned with the conductive layer to deposit a flux material in the second openings over the conductive layer.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: February 27, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Takashi Noma, Kazuhiro Saito
  • Publication number: 20180053739
    Abstract: A semiconductor wafer has an edge support ring around a perimeter of the semiconductor wafer and conductive layer formed over a surface of the semiconductor wafer within the edge support ring. A first stencil is disposed over the edge support ring with first openings aligned with the conductive layer. The first stencil includes a horizontal portion over the edge support ring, and a step-down portion extending the first openings to the conductive layer formed over the surface of the semiconductor wafer. The horizontal portion may have a notch with the edge support ring disposed within the notch. A plurality of bumps is dispersed over the first stencil to occupy the first openings over the conductive layer. A second stencil is disposed over the edge support ring with second openings aligned with the conductive layer to deposit a flux material in the second openings over the conductive layer.
    Type: Application
    Filed: August 18, 2016
    Publication date: February 22, 2018
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. SEDDON, Takashi NOMA, Kazuhiro SAITO
  • Publication number: 20180005951
    Abstract: A method of forming semiconductor devices includes providing a wafer having a first side and second side, electrically conductive pads at the second side, and an electrically insulative layer at the second side with openings to the pads. The first side of the wafer is background to a desired thickness and an electrically conductive layer is deposited thereon. Nickel layers are simultaneously electrolessly deposited over the electrically conductive layer and over the pads, and diffusion barrier layers are then simultaneously deposited over the nickel layers. Another method of forming semiconductor devices includes depositing backmetal (BM) layers on the electrically conductive layer including a titanium layer, a nickel layer, and/or a silver layer. The BM layers are covered with a protective coating and a nickel layer is electrolessly deposited over the pads. A diffusion barrier layer is deposited over the nickel layer over the pads, and the protective coating is removed.
    Type: Application
    Filed: March 2, 2017
    Publication date: January 4, 2018
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yusheng LIN, Takashi NOMA, Shinzo ISHIBE
  • Patent number: 9748032
    Abstract: An inductor array chip includes a magnetic laminated body and a plurality of inductors. The magnetic laminated body includes a plurality of stacked magnetic layers. The plurality of inductors are arranged inside the magnetic laminated body. The inductance of a first inductor differs from the inductance of a second inductor. The inductors include a plurality of coil-shaped conductors and via-hole conductors. The plurality of coil-shaped conductors are arranged between the magnetic layers. The via-hole conductors electrically connect the plurality of coil-shaped conductors. The inductors include a plurality of inductors in which the section sizes of the coil-shaped conductors differ from one another.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: August 29, 2017
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yoshihiro Kubota, Takashi Noma
  • Publication number: 20170222563
    Abstract: A power supply module includes a substrate, a switching control IC and a coil. The coil includes a plurality of metal posts, first ends of which are mounted on a first surface of the substrate, wiring conductors that are in conductive contact with the first ends of the metal posts, and post connection conductors that are in conductive contact with second ends of the metal posts. The power supply module further includes a magnetic core that strengthens magnetic flux generated by the coil, and a sealing resin that seals the metal posts and the magnetic core.
    Type: Application
    Filed: April 14, 2017
    Publication date: August 3, 2017
    Inventors: Takashi NOMA, Keiichi ICHIKAWA
  • Patent number: 9666356
    Abstract: In a common-mode choke coil, first annular conductors are helically defined from the lower layer to the upper layer, and first annular conductors are helically defined from the upper layer to the lower layer. Further, second annular conductors are helically defined from the lower layer to the upper layer, and second annular conductors are helically defined from the upper layer to the lower layer. The first annular conductors and the second annular conductors are disposed alternately in a lamination direction. The first annular conductors and the second annular conductors are disposed such that substantial portions of the annular conductors adjacent to each other in the layer direction do not overlap in a planar view. This structure achieves a compact common-mode choke coil with which the loss of normal-mode signals is small, and which is highly capable of removing common-mode noise.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: May 30, 2017
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Noboru Kato, Takashi Noma, Hisashi Akiyama
  • Patent number: 9640497
    Abstract: A method of forming semiconductor devices includes providing a wafer having a first side and second side, electrically conductive pads at the second side, and an electrically insulative layer at the second side with openings to the pads. The first side of the wafer is background to a desired thickness and an electrically conductive layer is deposited thereon. Nickel layers are simultaneously electrolessly deposited over the electrically conductive layer and over the pads, and diffusion barrier layers are then simultaneously deposited over the nickel layers. Another method of forming semiconductor devices includes depositing backmetal (BM) layers on the electrically conductive layer including a titanium layer, a nickel layer, and/or a silver layer. The BM layers are covered with a protective coating and a nickel layer is electrolessly deposited over the pads. A diffusion barrier layer is deposited over the nickel layer over the pads, and the protective coating is removed.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: May 2, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yusheng Lin, Takashi Noma, Shinzo Ishibe
  • Patent number: 9627759
    Abstract: An antenna device includes a multilayer body as a base body, an antenna coil, and a capacitor chip. The multilayer body includes a magnetic layer including a first main surface and a second main surface, a first non-magnetic layer provided on the first main surface of the magnetic layer, and a second non-magnetic layer provided on the second main surface of the magnetic layer. The antenna coil includes a first coil pattern provided with the first non-magnetic layer and a second coil pattern provided with the second non-magnetic layer. The capacitor chip is connected to the antenna coil and provided on the second non-magnetic layer.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: April 18, 2017
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Noboru Kato, Takashi Noma, Kuniaki Yosui
  • Patent number: 9373441
    Abstract: A composite electronic component with a built-in coil is provided which can be produced inexpensively, which can effectively increase insulating reliability, and which has the antistatic function. Coil wirings are disposed inside a sintered body that is formed by stacking a plurality of ferrite layers, which are fired as an integral unit. Voltage nonlinear members are incorporated in the sintered body at a different height position from those of the coil wirings. First inner electrodes and second inner electrodes are disposed in opposing relation with the voltage nonlinear members interposed therebetween. A magnetic circuit forming portion is constituted by a part of the ferrite layers and the coil wirings in a portion in which the coil wirings are arranged, and an antistatic portion is constituted in a portion in which the remaining ferrite layers, the voltage nonlinear members, and the first and second inner electrodes are arranged.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: June 21, 2016
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Takashi Noma, Tetsuya Ikeda
  • Patent number: 9320184
    Abstract: An ESD protection device includes an alumina multilayer substrate, a hollow portion, a discharge electrode pair, discharge-assisting electrodes, and a vitreous substance. The hollow portion is disposed inside of the alumina multilayer substrate. The electrodes of the discharge electrode pair are disposed opposite to each other at an interface between the hollow portion and the alumina multilayer substrate. The discharge-assisting electrodes are disposed dispersedly between the opposite electrodes of the discharge electrode pair. The vitreous substance covers the discharge-assisting electrodes in the inside of the hollow portion. A trial discharge is executed so as to induce creepage discharge between the electrodes of the discharge electrode pair in advance.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: April 19, 2016
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kosuke Yamada, Takashi Noma, Jun Adachi
  • Publication number: 20160104569
    Abstract: In a common-mode choke coil, first annular conductors are helically defined from the lower layer to the upper layer, and first annular conductors are helically defined from the upper layer to the lower layer. Further, second annular conductors are helically defined from the lower layer to the upper layer, and second annular conductors are helically defined from the upper layer to the lower layer. The first annular conductors and the second annular conductors are disposed alternately in a lamination direction. The first annular conductors and the second annular conductors are disposed such that substantial portions of the annular conductors adjacent to each other in the layer direction do not overlap in a planar view. This structure achieves a compact common-mode choke coil with which the loss of normal-mode signals is small, and which is highly capable of removing common-mode noise.
    Type: Application
    Filed: December 16, 2015
    Publication date: April 14, 2016
    Inventors: Noboru KATO, Takashi NOMA, Hisashi AKIYAMA
  • Publication number: 20160043469
    Abstract: To ensure a sufficient communication distance and to concurrently suppress a conductor loss, a coil antenna includes a magnetic core including a first peripheral surface including at least a first principal surface, a first coil conductor located on the first principal surface and wound around a predetermined winding axis, a first base material layer stacked on the first principal surface, including at least a first surface parallel or substantially parallel to the first principal surface, and made of a material having a lower magnetic permeability than the magnetic core, and a second coil conductor located on at least the first surface. Opposite ends of the second coil conductor are coupled to the first coil conductor on the first principal surface, and a direction in which a current flows through the first coil conductor on the first principal surface is substantially the same as a direction in which a current flows through the second coil conductor on the first surface.
    Type: Application
    Filed: October 21, 2015
    Publication date: February 11, 2016
    Inventors: Nobuhito TSUBAKI, Takashi NOMA, Noboru KATO
  • Patent number: 9245681
    Abstract: In a common-mode choke coil, first annular conductors are helically defined from the lower layer to the upper layer, and first annular conductors are helically defined from the upper layer to the lower layer. Further, second annular conductors are helically defined from the lower layer to the upper layer, and second annular conductors are helically defined from the upper layer to the lower layer. The first annular conductors and the second annular conductors are disposed alternately in a lamination direction. The first annular conductors and the second annular conductors are disposed such that substantial portions of the annular conductors adjacent to each other in the layer direction do not overlap in a planar view. This structure achieves a compact common-mode choke coil with which the loss of normal-mode signals is small, and which is highly capable of removing common-mode noise.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: January 26, 2016
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Noboru Kato, Takashi Noma, Hisashi Akiyama
  • Patent number: 9214728
    Abstract: To ensure a sufficient communication distance and to concurrently suppress a conductor loss, a coil antenna includes a magnetic core including a first peripheral surface including at least a first principal surface, a first coil conductor located on the first principal surface and wound around a predetermined winding axis, a first base material layer stacked on the first principal surface, including at least a first surface parallel or substantially parallel to the first principal surface, and made of a material having a lower magnetic permeability than the magnetic core, and a second coil conductor located on at least the first surface. Opposite ends of the second coil conductor are coupled to the first coil conductor on the first principal surface, and a direction in which a current flows through the first coil conductor on the first principal surface is substantially the same as a direction in which a current flows through the second coil conductor on the first surface.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: December 15, 2015
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Nobuhito Tsubaki, Takashi Noma, Noboru Kato
  • Publication number: 20150302980
    Abstract: A composite electronic component with a built-in coil is provided which can be produced inexpensively, which can effectively increase insulating reliability, and which has the antistatic function. Coil wirings are disposed inside a sintered body that is formed by stacking a plurality of ferrite layers, which are fired as an integral unit. Voltage nonlinear members are incorporated in the sintered body at a different height position from those of the coil wirings. First inner electrodes and second inner electrodes are disposed in opposing relation with the voltage nonlinear members interposed therebetween. A magnetic circuit forming portion is constituted by a part of the ferrite layers and the coil wirings in a portion in which the coil wirings are arranged, and an antistatic portion is constituted in a portion in which the remaining ferrite layers, the voltage nonlinear members, and the first and second inner electrodes are arranged.
    Type: Application
    Filed: April 16, 2014
    Publication date: October 22, 2015
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Takashi NOMA, Tetsuya IKEDA
  • Patent number: 9129718
    Abstract: A X-ray waveguide includes a core for guiding X-rays having a wavelength band in which the real part of refractive index of material is smaller than 1 and a cladding for confining the X-rays in the core. The core has a one-dimensional periodic structure in which a plurality of layers respectively formed of inorganic materials having different real parts of refractive index are periodically laminated. The core and the cladding are configured so that a critical angle for total reflection for the X-rays at an interface between the core and the cladding is larger than a Bragg angle due to a periodicity of the one-dimensional periodic structure. A critical angle for total reflection for the X-rays at an interface between layers in the one-dimensional periodic structure is smaller than the Bragg angle due to the periodicity of the one-dimensional periodic structure.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: September 8, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kohei Okamoto, Atsushi Komoto, Wataru Kubo, Hirokatsu Miyata, Takashi Noma
  • Publication number: 20150221428
    Abstract: An inductor array chip includes a magnetic laminated body and a plurality of inductors. The magnetic laminated body includes a plurality of stacked magnetic layers. The plurality of inductors are arranged inside the magnetic laminated body. The inductance of a first inductor differs from the inductance of a second inductor. The inductors include a plurality of coil-shaped conductors and via-hole conductors. The plurality of coil-shaped conductors are arranged between the magnetic layers. The via-hole conductors electrically connect the plurality of coil-shaped conductors. The inductors include a plurality of inductors in which the section sizes of the coil-shaped conductors differ from one another.
    Type: Application
    Filed: April 14, 2015
    Publication date: August 6, 2015
    Inventors: Yoshihiro KUBOTA, Takashi NOMA
  • Patent number: 9034729
    Abstract: An object of the invention is to provide a smaller semiconductor device of which the manufacturing process is simplified and the manufacturing cost is reduced and a method of manufacturing the same. Furthermore, an object of the invention is to provide a semiconductor device having a cavity. A first supporting body 5 having a penetration hole 6 penetrating it from the front surface to the back surface is attached to a front surface of a semiconductor substrate 2 with an adhesive layer 4 being interposed therebetween. A device element 1 and wiring layers 3 are formed on the front surface of the semiconductor substrate 2. A second supporting body 7 is attached to the first supporting body 5 with an adhesive layer 8 being interposed therebetween so as to cover the penetration hole 6. The device element 1 is sealed in a cavity 9 surrounded by the semiconductor substrate 2, the first supporting body 5 and the second supporting body 7.
    Type: Grant
    Filed: August 22, 2007
    Date of Patent: May 19, 2015
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Hiroshi Yamada, Katsuhiko Kitagawa, Kazuo Okada, Yuichi Morita, Hiroyuki Shinogi, Shinzo Ishibe, Yoshinori Seki, Takashi Noma
  • Patent number: 9031189
    Abstract: An X-ray imaging apparatus acquiring a differential phase contrast image of a test object without using a light-shielding mask for X-ray. The apparatus includes an X-ray source, a splitting element configured to spatially divide an X-ray emitted from an X-ray source and a scintillator configured to emit light when a divided X-ray beam divided at the splitting element is incident on the scintillator. The apparatus also includes a light-transmission limiting unit configured to limit transmitting amount of the light emitted from the scintillator and a plurality of light detectors each configured to detect the amount of light that has transmitted through the light-transmission limiting unit. The light-transmission limiting unit is configured such that a light intensity detected at each of the light detectors changes in response to a change in an incident position of the X-ray beam.
    Type: Grant
    Filed: January 27, 2011
    Date of Patent: May 12, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Taihei Mukaide, Takashi Noma, Kazunori Fukuda, Masatoshi Watanabe, Kazuhiro Takada
  • Publication number: 20150079273
    Abstract: An ESD protection device includes an alumina multilayer substrate, a hollow portion, a discharge electrode pair, discharge-assisting electrodes, and a vitreous substance. The hollow portion is disposed inside of the alumina multilayer substrate. The electrodes of the discharge electrode pair are disposed opposite to each other at an interface between the hollow portion and the alumina multilayer substrate. The discharge-assisting electrodes are disposed dispersedly between the opposite electrodes of the discharge electrode pair. The vitreous substance covers the discharge-assisting electrodes in the inside of the hollow portion. A trial discharge is executed so as to induce creepage discharge between the electrodes of the discharge electrode pair in advance.
    Type: Application
    Filed: November 25, 2014
    Publication date: March 19, 2015
    Inventors: Kosuke YAMADA, Takashi NOMA, Jun ADACHI