Abstract: A DCDC converter includes a signal splitting unit that splits an input signal into N signal components; N DCDC converter elements that process individually the N split signals; and an adder that adds outputs from the plural DCDC converter elements to generate output signals. Each of the DCDC converter elements has an operation band narrower than an applicable frequency band of the input signal, and selects a design parameter that allows a conversion efficiency of the DCDC converter elements to be optimized for any band of the applicable frequency bands. For example, the parameter of a PMOS transistor and a NMOS transistor, which configure an inverter is designed to optimize the efficiency at any of frequency bands. The frequency band of the input signal is split, and each of the split outputs is input to a DCDC converter element that has a corresponding frequency and high efficiency characteristic.

Abstract: A logical level converter generates an output signal by which a succeeding logical circuit accurately operates even if there is a threshold fluctuation factor. In the logical level converter, an output signal of a voltage control oscillator in a phase locked loop is inputted to a threshold variable inverter. A DC component of another output signal from the threshold variable inverter is inputted to a comparator, and compared with a comparison voltage. A threshold setting signal is outputted on the basis of a comparison result. The threshold value of the threshold variable inverter is changed according to the threshold variable signal, and the output signal is converted into the other output signal. When the comparison result comes to a given state, the value of the threshold setting signal is held, and the other output signal is outputted as a further different output signal.

Abstract: A semiconductor device includes a transfer section which receives, from an external source, a second program for modifying a function of a first program stored in a read-only memory (ROM) and information required in activation of the second program, and which writes the program and the information to a nonvolatile semiconductor memory, and a load section which activates the second program on the basis of the information written to the nonvolatile semiconductor memory to modify the function of the first program.

Abstract: A nonvolatile semiconductor memory includes a storage area including of a plurality of data blocks and a management block which stores management information related to a storage medium in a lump. The storage area is divided into a plurality of areas and each area has a data block containing a particular page which stores information indicating whether or not the management block is present in the area.

Abstract: A controller comprises a host interface section and a processing circuit. The host interface section receives a command sequence outputted from a host apparatus to a first nonvolatile semiconductor memory. The processing circuit processes the command sequence outputted from the host apparatus to the first nonvolatile semiconductor memory, and controls writing, reading and erase of data to a second nonvolatile semiconductor memory, according to the command sequence.

Abstract: A semiconductor device includes a transfer section which receives, from an external source, a second program for modifying a function of a first program stored in a read-only memory (ROM) and information required in activation of the second program, and which writes the program and the information to a nonvolatile semiconductor memory, and a load section which activates the second program on the basis of the information written to the nonvolatile semiconductor memory to modify the function of the first program.

Abstract: A semiconductor device includes a controller which operates if a request is made that data be written in a certain area in a first block in a semiconductor memory having a predetermined erase block size in which data has already been written, to write the data requested to be written, in a leading area in a second block from which data has already been erased, regardless of a value of an address of the certain area.

Abstract: A memory system, which is connected to a host device, includes a memory, a host interface which receives a command and an address, which are output from the host device, and a controller which operates in one of a first mode in which the controller converts the address which is received by the host interface and accesses the memory by using the converted address, and a second mode in which the host device directly accesses the memory by using the address which is received by the host interface, the controller controlling switching between the first mode and second mode in accordance with the command.

Abstract: A semiconductor device includes a controller which operates if a request is made that data be written in a certain area in a first block in a semiconductor memory having a predetermined erase block size in which data has already been written, to write the data requested to be written, in a leading area in a second block from which data has already been erased, regardless of a value of an address of the certain area.

Abstract: A memory system for transmitting data to and receiving data from a host apparatus includes a semiconductor memory and an access-controlling part. The semiconductor memory has storage areas identified by physical addresses, stores data in each of the storage areas, performs data write in accordance with a request made by the host apparatus. The access-controlling part selects a recommended address, which is recommended to be used in a next data write, on the basis of operation information about a factor that influences time consumed for data write in the semiconductor memory, and outputs the recommended address to the host apparatus.

Abstract: A memory unit includes a plurality of first blocks each having a first block size. Each of the first blocks stores data of a plurality of second blocks each having a second block size which is smaller than the first block size. A control unit writes the data of the second block in the first block. The control unit is configured such that in a case where the second block to be written is a block that is to be written in the same first block as the second block that is already written in the first block, the second block to be written is written in the same first block even if an address of the second block to be written is not consecutive to an address of the second block that is already written in the first block.

Abstract: Each of a plurality of memory areas includes a plurality of blocks. Each of the blocks includes a plurality of pages. Each of the memory areas also includes a data cache and a page buffer. A control unit controls a lower-limit value of the number of empty blocks in each of the plurality of memory areas.

Abstract: A semiconductor device includes a volatile memory and a controller which stores address conversion information in the volatile memory and execute an address converting process using the address conversion information, the address conversion information indicating some of all correspondences between addresses in a first semiconductor memory having a first erase block size and addresses in a second semiconductor memory having a second erase block size different from the first erase block size.

Abstract: A device which is capable of storing moving picture data received from each terminal and providing each terminal with video information to be reproducible by rapidly forwarding or reversing at any desired speed independent of usable terminals. A video storage type communication device 30 with a receiving portion 35 and a transmitting portion 38 transmits and receives video data over a communication network 10 to and from each terminal 1–n. A coded video data received from terminals 1–n is stored as it is in a first storage portion 32 and, at the same time, the data converted into specially reproducible video information is stored in the second storage portion 33. At the time of reproducing, the reproduction control portion 35 controls the reproduction selector switch 36 to obtain the video data from the first storage portion 32 or the second storage portion 33, changing the reproduction mode from ordinary to the rapid forwarding/reversing and vice versa.

Abstract: There is disclosed a memory having a plurality of blocks including management information, and a centralized management block in which the management information of each block is centralized, wherein a control section detects the centralized management block in the memory at a starting time, and searches for the management information from the plurality of blocks in the memory, and writes the searched management information into the centralized management block of the memory, within a restricted time set in a system in a case where the centralized management block includes an error.

Abstract: A nonvolatile semiconductor memory includes a storage area including of a plurality of data blocks and a management block which stores management information related to a storage medium in a lump. The storage area is divided into a plurality of areas and each area has a data block containing a particular page which stores information indicating whether or not the management block is present in the area.

Abstract: A logical level converter generates an output signal by which succeeding logical circuit accurately operates even if there is a threshold fluctuation factor. In the logical level converter, an output signal of a voltage control oscillator in a phase locked loop is inputted to a threshold variable inverter. A DC component of another output signal from the threshold variable inverter is inputted to a comparator, and compared with a comparison voltage. A threshold setting signal is outputted on the basis of a comparison result. The threshold value of the threshold variable inverter is changed according to the threshold variable signal, and the output signal is converted into the other output signal. When the comparison result comes to a given state, the value of the threshold setting signal is held, and the other output signal is outputted as a further different output signal.

Abstract: A variable loop bandwidth phase locked loop in which, upon input of a succession of signals “1”, no modulated signal degradation occurs and even at a high symbol rate, the reference signal frequency remains low and the sampling frequencies of a phase-frequency detector and a sigma delta circuit remain low. The phase locked loop comprises: a first modulator which transforms baseband signal TX_DATA into an integer signal for specifying a division number and sends it to a control terminal of a programmable divider; a second modulator which shapes an incoming baseband signal into a prescribed signal waveform and sends it to a voltage controlled oscillator; and a variable current charge pump which changes the loop bandwidth of the phase locked loop according to control signal CUR.

Abstract: A memory card includes a first memory including first areas and second areas. A computing section gives an instruction to write writing data with an address assigned by a host unit into the first memory. A second memory stores an address unequal to an expected value. The address with the expected value is continuous with the address of the data last written. A first counter counts a number of requests to write the writing data of the address unequal to the expected value for each of the addresses. A third memory stores the address whose value in the first counter has reached a first set value. When receiving a request to write the writing data of the address stored in the third memory, the computing section gives an instruction to write the writing data into an unwritten part of the second areas, regardless of the address.

Abstract: Plural second logic blocks are set to a first logic block, and when data is written to the second logic block, write waiting is given using an address next to the address of the current second logic block. In order to protect data of the written second logic block, the next address is skipped using another address as an expected value.