Abstract: A semiconductor memory device includes a sense amplifier, first and second bit lines connected to the sense amplifier, a first reference cell connected to the first bit line, and a second reference cell connected to the second bit line. A reference potential is simultaneously written to the first and second reference cells. Further, a dummy cell may be provided to be simultaneously, with the reference cell, with the reference potential.

Abstract: In a semiconductor device including a memory region and a logic region, one or more of a plurality of logic transistor connection plugs, buried in a first insulating layer and connected to a diffusion layer of a logic transistor, are left unconnected to a first interconnect provided in an upper layer.

Abstract: A semiconductor memory device has bit lines, capacitors, bit contacts and capacitor contacts, wherein the bit lines are provided over a semiconductor substrate, the bit lines are connected to the semiconductor substrate through the bit contacts, the capacitors are connected to the semiconductor substrate through the capacitor contacts, and wherein in two adjacent bit lines, pitch d2 (first pitch) representing a pitch of portions provided with the capacitor contacts is larger than pitch d3 (second pitch) representing a pitch of portions provided with the bit contacts, and distance d4 between two such bit lines in the portions provided with the bit contacts is larger than width d5 of the bit lines in the portions provided with the bit contacts.

Abstract: When the film thickness of an insulating film on a fuse connected to a circuit is not uniform within a wafer surface, there was a problem that disconnection of the fuse might become insufficient due to the insufficient intensity of a laser or disconnection of even an adjacent fuse due to excessive laser irradiation might occur. Further, a problem also occurred that after disconnection of the fuse, moisture entered from exterior through the region in which the fuse has been disconnected, so that the quality of a film underlying the fuse was adversely affected. After a SiON film, a SiN film, and a SiO2 film have been formed to cover the fuse in this stated order, etching is performed to the SiN film, which is an etching stopper film. The SiON film having a uniform and desired film thickness is thereby formed on the fuse.

Abstract: In a conventional semiconductor device, an excessive etching occurs in a section where an opening for contact plug is formed, causing a damage to a diffusion layer located under the opening. A semiconductor device 1 includes a region D1 for forming an electric circuit, and a seal ring 30 (guard ring) that surrounds the region D1 for forming the electric circuit. A DRAM 40 is formed in the region D1 for forming the electric circuit. Interlayer insulating films 22, 24, 26 and 28 are formed on a semiconductor substrate 10. The seal ring 30 is formed in the interlayer insulating films 22, 24, 26 and 28, and at least a portion there of is located spaced apart from the semiconductor substrate 10.

Abstract: The present invention solves a problem of the degradation of the long-term reliability of a conventional semiconductor memory device due to early deterioration of a FET included in a reference cell therein. DRAM 1 has word lines 101 to 10n, word lines 22 and 24, memory cells 301 to 30n and a reference cell 40. Gates of FETs 32 in the memory cells 301 to 30n are connected to the word lines 101 to 10n respectively. Gates of a FET 42 and a FET 44 in the reference cell 40 are connected to the word line 22 for readout and the word line 24 for writing respectively. Here, potentials applied to the word lines 22 and 24 are lower than those applied to the word lines 101 to 10n.

Abstract: When the film thickness of an insulating film on a fuse connected to a circuit is not uniform within a wafer surface, there was a problem that disconnection of the fuse might become insufficient due to the insufficient intensity of a laser or disconnection of even an adjacent fuse due to excessive laser irradiation might occur. Further, a problem also occurred that after disconnection of the fuse, moisture entered from exterior through the region in which the fuse has been disconnected, so that the quality of a film underlying the fuse was adversely affected. After a SiON film, a SiN film, and a SiO2 film have been formed to cover the fuse in this stated order, etching is performed to the SiN film, which is an etching stopper film. The SiON film having a uniform and desired film thickness is thereby formed on the fuse.

Abstract: A memory region including a capacitor element, a logic region including a logic circuit, and a boundary region located between the memory region and the logic region are provided on a silicon substrate. The memory region includes a plurality of memory transistors and memory transistor connection plugs. The boundary region includes a dummy contact plug in the same layer as the memory transistor connection plugs and logic transistor connection plugs. The upper face of the dummy contact plug is covered with a second insulating layer. An end portion of a capacitor layer and an upper electrode is located closer to an inner region of the memory region than the dummy contact plug is.

Abstract: There is provided a semiconductor chip having fuses. The semiconductor chip includes fuses each having a first terminal electrically connected to a first logic circuit, a second terminal electrically connected to a second logic circuit, and a blowable region formed between the first terminal and the second terminal; and fuse residues each having the same patterns with those of the first terminal and the second terminal of the fuses, and configured so that patterns corresponded to the first terminals and the second terminals are electrically disconnected from each other.

Abstract: A memory region including a capacitor element, a logic region including a logic circuit, and a boundary region located between the memory region and the logic region are provided on a silicon substrate. The memory region includes a plurality of memory transistors and memory transistor connection plugs. The boundary region includes a dummy contact plug in the same layer as the memory transistor connection plugs and logic transistor connection plugs. The upper face of the dummy contact plug is covered with a second insulating layer. An end portion of a capacitor layer and an upper electrode is located closer to an inner region of the memory region than the dummy contact plug is.

Abstract: In a semiconductor device including a memory region and a logic region, one or more of a plurality of logic transistor connection plugs, buried in a first insulating layer and connected to a diffusion layer of a logic transistor, are left unconnected to a first interconnect provided in an upper layer.

Abstract: When the film thickness of an insulating film on a fuse connected to a circuit is not uniform within a wafer surface, there was a problem that disconnection of the fuse might become insufficient due to the insufficient intensity of a laser or disconnection of even an adjacent fuse due to excessive laser irradiation might occur. Further, a problem also occurred that after disconnection of the fuse, moisture entered from exterior through the region in which the fuse has been disconnected, so that the quality of a film underlying the fuse was adversely affected. After a SiON film, a SiN film, and a SiO2 film have been formed to cover the fuse in this stated order, etching is performed to the SiN film, which is an etching stopper film. The SiON film having a uniform and desired film thickness is thereby formed on the fuse.

Abstract: A semiconductor memory device comprises memory cells in rows and columns. Each memory is of the capacitor type and includes one portion of a dielectric layer. Antifuse-components are connected in series one after another between a power source electrode and an output terminal that is grounded when a MOS transistor is conductive.

Abstract: A semiconductor memory device comprises memory cells in rows and columns. Each memory is of the capacitor type and includes one portion of a dielectric layer. Antifuse-components are connected in series one after another between a power source electrode and an output terminal that is grounded when a MOS transistor is conductive.

Abstract: Comparing with, for example, a semiconductor device having the configuration in which the logic circuit and the DRAM cell circuit are consolidated, a semiconductor device in which an analog capacity element is installed without substantially increasing the number of the steps is provided. An analog capacity element to be installed in the DNA e11 circuit has a structure in which a lower electrode 5, a side-wall insulation film 9, and a bit line are formed using the same materials and the same patterns as those of a gate electrode 4, a dielectric film 10, and bit line, respectively.

Abstract: In a semiconductor device, a polycrystalline silicon layer is formed on a semiconductor substrate, and an HSG polycrystalline silicon layer is formed on the polycrystalline silicon layer. The HSG polycrystalline silicon is converted from an amorphous silicon layer.

Abstract: Comparing with, for example, a semiconductor device having the configuration in which the logic circuit and the DRAM cell circuit are consolidated, a semiconductor device in which an analog capacity element is installed without substantially increasing the number of the steps is provided.

Abstract: A DRAM has a plurality of memory cells each including memory cell transistor and a peripheral circuit having a resistor element. The resistor element formed from a common layer with a contact plug in contact with the diffused regions of the cell transistor is disposed on a dummy pattern formed from common layer with the gate electrode of the cell transistor. The equal level for the resistor element and the contact plug provides an excellent fine patterning, thereby reducing the chip size of the DRAM.

Abstract: A partial one-shot exposure mask is provided for exposure, by repeating the patterns, of a photo-resist formed over active and isolation regions of a semiconductor device, wherein boundaries of patterns of the partial one-shot exposure mask are positioned only in the isolation region. The patterns of the partial one-shot exposure mask may be for formation of word lines. In this case, the boundaries of the patterns of the partial one-shot exposure mask may be formed in a direction perpendicular to a longitudinal direction of the word lines. Alternatively, the boundaries of the patterns of the partial one-shot exposure mask may be formed in a direction parallel to an active region. All of regions for formations of contact holes are included in the active region.

Abstract: An integrated circuit pattern lithography system comprises a repeat unit candidate generating section of extracting a repeat pattern area and further extracting pattern data and array data of a minimum unit of repeated patterns in the repeat pattern area, for generating repeat unit candidates formed by the array of a plurality of the minimum repeat units, a repeat unit deciding section for deciding a repeat unit to be arrayed in the whole repeat pattern area, from the generated repeat unit candidate group, and a cell projection mask manufacturing section for manufacturing a cell projection mask for use in partial batch exposure in the repeat pattern area, correspondingly to the decided repeat unit.