Abstract: A method of manufacturing a semiconductor memory device, comprising the steps of: forming a gate electrode with an insulating spacer, forming a first silicon oxide film by high-temperature chemical vapor deposition (CVD), forming n-type source/drain regions, forming a first insulating interlayer and forming a bit line; forming a second silicon oxide film by low-temperature CVD, forming a BPSG film, and annealing the second silicon oxide film and the BPSG film by first annealing to form a second insulating interlayer constituted by the stacked films; forming a third silicon oxide film by low-temperature CVD, and annealing the third silicon oxide film by second annealing; forming a node contact hole through the annealed third silicon oxide film, the second insulating interlayer, the first insulating interlayer, and the first silicon oxide film; forming an amorphous silicon film doped n-type at the time of the film formation, patterning the amorphous silicon film to form an amorphous silicon film pattern, and re

Abstract: There is provided a semiconductor device and a method for manufacturing the same wherein a capacitor stack is not separated from a substrate even when a shift in setting occurs between a contact and a stack pattern, and even when the stack pattern has a small size. After a contact hole is opened in an interlayer insulating film, a first polysilicon film which constitutes a storage electrode and a first BPSG film which constitutes a core are formed, one after another. Then a stack pattern is formed by patterning the first BPSG film and the first polysilicon film. A second polysilicon film is formed on a side wall of the stack pattern. Next, a second insulating BPSG film is formed on the overall surface of the silicon substrate, so that the upper surface of the second insulating film is located at a position higher than the upper surface of the stack pattern. After that, the second BPSG film is etched and removed until the upper surface of the first BPSG film of the core is exposed.

Abstract: A lower-level conductor layer is formed in a surface of, on or over a semiconductor substrate. An interlayer insulator film is formed on the lower-level conductor layer. An upper-level conductor layer such as an interconnection layer of the semiconductor device is formed on the interlayer insulator film. A conductor plug is formed in a contact hole of the interlayer insulator film. The lower-level conductor layer and the upper-level conductor layer are electrically connected with each other through the conductor plug. A top part of the conductor plug protrudes from the interlayer insulator film. The upper-level conductor layer is contacted with a top face and a side face of the top part of the conductor plug. Both the contact resistance between the conductor contact and the upper-level conductor layer and the resistance of the upper-level conductor layer itself can be reduced without using a special equipment and a special process.