Patents by Inventor Takashi Shigematsu

Takashi Shigematsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120052675
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Application
    Filed: November 8, 2011
    Publication date: March 1, 2012
    Applicants: HITACHI ULSI SYSTEMS CO., LTD., RENESAS ELECTRONICS CORPORATION
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Patent number: 8076202
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Grant
    Filed: March 15, 2010
    Date of Patent: December 13, 2011
    Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Publication number: 20110215398
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Application
    Filed: May 13, 2011
    Publication date: September 8, 2011
    Applicants: RENESAS ELECTRONICS CORPORATION, HITACHI ULSI SYSTEMS CO., LTD.
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Publication number: 20100203231
    Abstract: Disclosed is a method of producing an insulated electric wire, in which a primary coating layer including at least an enamel-baking layer is formed on a metallic conductor to form a primary coated electric wire, and a secondary coating layer is extrusion-formed on the primary coating layer of the primary coated electric wire. The method includes an electric wire pre-heating process where a surface of the primary coating layer is pre-heated using an electric wire pre-heating unit, and a resin extrusion process where a secondary coating layer is extrusion-formed on the pre-heated primary coating layer using a resin extrusion unit. Further disclosed is an apparatus for producing an insulated electric wire.
    Type: Application
    Filed: March 28, 2008
    Publication date: August 12, 2010
    Inventors: Hiroyuki Kusaka, Koji Kuromiya, Satoshi Saito, Takashi Shigematsu, Akihiro Murakami, Shinji Ichikawa, Haruo Sakuma, Shingo Nishijima
  • Publication number: 20100173461
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Application
    Filed: March 15, 2010
    Publication date: July 8, 2010
    Applicants: RENESAS TECHNOLOGY CORP., HITACHI ULSI SYSTEMS CO., LTD.
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Patent number: 7343068
    Abstract: An optical module including first and second lens housings that individually receive first and second lenses; first and second optical fiber housings that individually receive end portions of optical fibers; first and second guide pins for positioning the first and second lens housings and the first and second optical fiber housings, with the first and second lens housings abutted against each other at their inner end faces and disposed between the first and second optical fiber units so as to be abutted thereto; two first positioning members provided between the first optical fiber housing and the first lens and between the second optical fiber housing and the second lens, respectively; and a second positioning member disposed between the first and second lenses.
    Type: Grant
    Filed: May 14, 2007
    Date of Patent: March 11, 2008
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Takashi Shigenaga, Katsuki Suematsu, Hiroshi Matsuura, Renichi Yuguchi, Takashi Shigematsu
  • Publication number: 20070290239
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Application
    Filed: July 27, 2007
    Publication date: December 20, 2007
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Publication number: 20070290268
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Application
    Filed: August 9, 2007
    Publication date: December 20, 2007
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Publication number: 20070278567
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Application
    Filed: August 3, 2007
    Publication date: December 6, 2007
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Publication number: 20070217741
    Abstract: An optical module including first and second lens housings that individually receive first and second lenses; first and second optical fiber housings that individually receive end portions of optical fibers; first and second guide pins for positioning the first and second lens housings and the first and second optical fiber housings, with the first and second lens housings abutted against each other at their inner end faces and disposed between the first and second optical fiber units so as to be abutted thereto; two first positioning members provided between the first optical fiber housing and the first lens and between the second optical fiber housing and the second lens, respectively; and a second positioning member disposed between the first and second lenses.
    Type: Application
    Filed: May 14, 2007
    Publication date: September 20, 2007
    Inventors: Takashi Shigenaga, Katsuki Suematsu, Hiroshi Matsuura, Renichi Yuguchi, Takashi Shigematsu
  • Publication number: 20070111423
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Application
    Filed: January 16, 2007
    Publication date: May 17, 2007
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakee Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Patent number: 7218811
    Abstract: An optical module includes first and second fiber units that hold end portions of first and second optical fibers, and first and second collimators disposed between these fiber units and having first and second lenses, respectively. End faces of the first and second optical fibers are disposed on imaginary circumferences on the end faces of the first and second fiber units. Laser light beams from the end face of the first optical fiber are collimated by the first lens and then focused by the second lens, and enter the end face of the second optical fiber that is disposed diametrically opposite to the first optical fiber with respect to the center axis of the optical module.
    Type: Grant
    Filed: January 6, 2003
    Date of Patent: May 15, 2007
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Takashi Shigenaga, Katsuki Suematsu, Hiroshi Matsuura, Renichi Yuguchi, Takashi Shigematsu
  • Patent number: 7180130
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: February 20, 2007
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Patent number: 6947636
    Abstract: An optical module comprises an optical fiber having a formed portion to form a fiber grating and a package to which the optical fiber is secured. The package comprises a single package member or at least two or more package members whose materials differ from each other. The optical fiber is secured to the package member. A distortion for adjusting a Bragg reflection wavelength of the fiber grating of the optical fiber is given to the package member.
    Type: Grant
    Filed: May 14, 2002
    Date of Patent: September 20, 2005
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Atsushi Shinozaki, Takashi Shigematsu, Toshihiko Ota, Shigehito Yodo
  • Publication number: 20050037579
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Application
    Filed: September 24, 2004
    Publication date: February 17, 2005
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Patent number: 6834143
    Abstract: An optical module comprising: a comb-shaped package having a plurality of teeth portions and a base portion; and at least one optical fiber having fiber grating, wherein respective fiber-grating formed portions of at least one optical fiber are placed in corresponding teeth portions and base portion of said package, and the optical fiber is fixed to the base portion and corresponding teeth portion in such manner that the fiber-grating formed portion exists between the base portion and the corresponding teeth portion.
    Type: Grant
    Filed: May 29, 2002
    Date of Patent: December 21, 2004
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Atsushi Shinozaki, Takashi Shigematsu, Toshihiko Ota, Shigehito Yodo
  • Patent number: 6803281
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Grant
    Filed: February 25, 2004
    Date of Patent: October 12, 2004
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Publication number: 20040166656
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Application
    Filed: February 25, 2004
    Publication date: August 26, 2004
    Applicants: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Patent number: 6767196
    Abstract: A manufacturing apparatus for multi-fiber optical ferrule includes a spacer whose hardness is equivalent to or higher than the hardness of pins for forming fiber holes. Further, corner portions with respect to the arrangement direction of the pins for forming fiber holes of the spacer are formed as inclined surfaces or rounded surfaces.
    Type: Grant
    Filed: January 22, 2002
    Date of Patent: July 27, 2004
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Jun Yamakawa, Masahiro Hirao, Yasushi Kihara, Takashi Shigematsu
  • Patent number: 6720220
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: April 13, 2004
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi