Abstract: A peak-hold circuit includes a differential amplifier having first and second transistors as a differential pair, the first transistor receiving an input signal at its gate, a third transistor connected between a first power supply and an output node connecting a gate of the second transistor, connectivity of the third transistor being controlled by the output of the differential amplifier, a capacitor for holding a peak voltage, connected between the output node and a second power supply, a resistor for discharging, which is connected in parallel to the capacitor, and a fourth transistor connected to the first transistor in parallel, the fourth transistor receiving at its gate an a reference voltage for limiting a voltage.

Abstract: In a receiver set, a shared receiver receives a signal formed according to one of various modulation or communication systems to output a received signal. A signal intensity detector detects the electric power value, or absolute value of the amplitude, of the received signal to output a detected signal. A determiner compares the magnitude of the detected signal with threshold voltages, and generates control signals to output them to switches. The switches are operated in response to the respective control signals fed to the switches so that the received signal is selectively fed to demodulators. The demodulators demodulate the received signal according to a receiving system corresponding to the modulation or transmission systems to output demodulated signals.

Abstract: In order to provide a variable gain amplifier of enhanced linearity and wide variable gain range, an AM-modulated signal reception circuit in which the noise of an input portion is reduced so as to improve the follow-up characteristic of an AGC circuit, and an AM-modulated signal detection circuit which produces an output precisely corresponding to a peak value envelope, the variable gain amplifier comprises a differential input amplifier which includes transistors T1 and T2 (in FIG. 8) constituting a differential pair, and a constant current circuit Is operating as an absorption current circuit of the transistors T1 and T2, and a variable impedance which is connected between the sources of the respective transistors T1 and T2, wherein the gain of the differential input amplifier is made variable by variably controlling the value of the variable impedance.

Abstract: An electronic device includes a wireless receiving circuit for receiving signals transmitted from a remote control unit, a core circuit having a digital signal processing circuit for processing input signals and configured to perform at least one of display processing and record processing based on signals processed in the digital signal processing circuit in accordance with a control signal transmitted from the remote control unit and received by the wireless receiving circuit, and a preliminary activation circuit for starting electric power supply to the digital signal processing circuit to thereby activate the digital signal processing circuit when a pre-operation state where the remote control unit is expected to be operated during stoppage of electric power supply to the core circuit has occurred.

Abstract: An analog semiconductor integrated circuit has an analog circuit, a PMOS and a bias adjustment circuit. The gate of the PMOS is the output section of an open drain system, and is connected to an internal node on the output side of the analog circuit. The bias adjustment circuit is connected to the internal node, and allows adjustment of the bias current in accordance with the fuse disconnection number. The relationship between the voltage when a fixed current flows to an input terminal and the fuse disconnection number that allows the optimum bias current to flow to the output section of the analog LSI is checked by using a plurality of sample analog LSIs having different threshold voltages. The voltage is measured by causing a fixed current to flow to the input terminal of a non-sample analog LSI, and the fuse disconnection number corresponding with this voltage is obtained. Thus, the fuses in the bias adjustment circuit are disconnected.

Abstract: The present invention aims to provide a reception frequency control circuit that is small in mounting area and unaffected by disturbance where an FSK-modulated signal is demodulated. In the reception frequency control circuit, a reception signal processing unit converts an FSK-modulated digital signal to an intermediate frequency when the FSK-modulated digital signal is received. Thereafter, a frequency voltage converting unit converts the intermediate signal to a voltage signal and outputs an output signal. At the same time, an analog frequency controlling unit detects a frequency deviation from the output signal by analog processing. A digital frequency controlling unit generates a reception frequency control signal for correcting the frequency and feeds back the same to the reception signal processing unit. Stable frequency control can be realized by performing reception frequency control by a combination of an analog circuit-digital circuit in this way.

Abstract: A wireless reception device, a wireless sending device, and a wireless transmitting device are provided, wherein occurrences of distortion and an error in the radio signal that is being transmitted can be prevented even if compensation for circuit characteristics is performed. The wireless reception device writes a reception parameter into reception parameter memory means for renewal, only when a predetermined renewal condition is satisfied. The wireless reception device generates a reception characteristic control signal, on the basis of a reception parameter which is stored in the reception parameter memory means. The wireless sending device writes a sending parameter into sending parameter memory means for renewal, only when a predetermined renewal condition is satisfied. The wireless sending device generates a sending characteristic control signal, on the basis of a sending parameter which is stored in sending parameter memory means.

Abstract: A wireless voice communication circuit includes an AD converter generating a first digital variable density signal from voice signal, and a first speed change circuit storing the first signal temporally in a first buffer and reading out it at a burst, a sending frame processing circuit generating a sending frame from the first signal, a modulator modulating and sending a frequency carrier in response to the sending frame, a demodulator demodulating a radio frequency signal received and outputting a receiving frame, a receiving frame processing circuit extracting a second digital variable density signal and outputting it together with a writing timing signal, a second speed change circuit writing the second signal in a second buffer temporally and reading out the signal stored in the second buffer at constant speed.

Abstract: A peak-hold circuit includes a differential amplifier having first and second transistors as a differential pair, the first transistor receiving an input signal at its gate, a third transistor connected between a first power supply and an output node connecting a gate of the second transistor, connectivity of the third transistor being controlled by the output of the differential amplifier, a capacitor for holding a peak voltage, connected between the output node and a second power supply, a resistor for discharging, which is connected in parallel to the capacitor, and a fourth transistor connected to the first transistor in parallel, the fourth transistor receiving at its gate an a reference voltage for limiting a voltage.

Abstract: In a receiver set, a shared receiver receives a signal formed according to one of various modulation or communication systems to output a received signal. A signal intensity detector detects the electric power value, or absolute value of the amplitude, of the received signal to output a detected signal. A determiner compares the magnitude of the detected signal with threshold voltages, and generates control signals to output them to switches. The switches are operated in response to the respective control signals fed to the switches so that the received signal is selectively fed to demodulators. The demodulators demodulate the received signal according to a receiving system corresponding to the modulation or transmission systems to output demodulated signals.

Abstract: In order to provide a variable gain amplifier of enhanced linearity and wide variable gain range, an AM-modulated signal reception circuit in which the noise of an input portion is reduced so as to improve the follow-up characteristic of an AGC circuit, and an AM-modulated signal detection circuit which produces an output precisely corresponding to a peak value envelope, the variable gain amplifier comprises a differential input amplifier which includes transistors T1 and T2 (in FIG. 8) constituting a differential pair, and a constant current circuit Is operating as an absorption current circuit of the transistors T1 and T2, and a variable impedance which is connected between the sources of the respective transistors T1 and T2, wherein the gain of the differential input amplifier is made variable by variably controlling the value of the variable impedance.

Abstract: An analog semiconductor integrated circuit has an analog circuit, a PMOS and a bias adjustment circuit. The gate of the PMOS is the output section of an open drain system, and is connected to an internal node on the output side of the analog circuit. The bias adjustment circuit is connected to the internal node, and allows adjustment of the bias current in accordance with the fuse disconnection number. The relationship between the voltage when a fixed current flows to an input terminal and the fuse disconnection number that allows the optimum bias current to flow to the output section of the analog LSI is checked by using a plurality of sample analog LSIs having different threshold voltages. The voltage is measured by causing a fixed current to flow to the input terminal of a non-sample analog LSI, and the fuse disconnection number corresponding with this voltage is obtained. Thus, the fuses in the bias adjustment circuit are disconnected.

Abstract: In order to provide a variable gain amplifier of enhanced linearity and wide variable gain range, an AM-modulated signal reception circuit in which the noise of an input portion is reduced so as to improve the follow-up characteristic of an AGC circuit, and an AM-modulated signal detection circuit which produces an output precisely corresponding to a peak value envelope, the variable gain amplifier comprises a differential input amplifier which includes transistors T1 and T2 (in FIG. 8) constituting a differential pair, and a constant current circuit Is operating as an absorption current circuit of the transistors T1 and T2, and a variable impedance which is connected between the sources of the respective transistors T1 and T2, wherein the gain of the differential input amplifier is made variable by variably controlling the value of the variable impedance.

Abstract: A bit position synchronizer including a sampling circuit which samples an input signal based on a plurality of phases of clock signals to obtain a plurality of sampled signals, a selector which selects one of the plurality of sampled signals, each of which is delayed for a short period, based on a selection signal and which outputs an output signal, a detection circuit which detects a first changing point and a second changing point of the sampled signals, a first register which stores a first value for the first changing point, a second register which stores a second value for the second changing point and a third register which stores an intermediate value between the first and second values and which outputs the selection signal.

Abstract: The feeder circuit to which the present invention pertains comprises means for regulating which serves to feed an electric current to a positive output terminal and a negative output terminal; means for feeding electric current which serves to feed an electric current to the means for regulating; means for regulator control which serves to control the electric current output from the means for regulating; a first resistance located between the negative terminal of the means for feeding electric current and the positive output terminal; and a second resistance located between the positive terminal of the means for feeding electric current and the negative output terminal.

Abstract: A tuning circuit includes an oscillator that receives an oscillating input signal and a control signal, and generates an oscillating output signal. The control signal is obtained from a frequency control circuit that compares the phases of the oscillating output signal and a reference signal. The control signal controls the transconductance of a transconductance element in the oscillator, thereby controlling the oscillator output frequency. The oscillating input signal is obtained from an amplitude control circuit that detects an amplitude limit of the oscillator output. The oscillator output amplitude is responsive to the oscillating input signal. Frequency control and amplitude control in this tuning circuit are mutually independent, so their respective control loops remain stable under all frequency and amplitude combinations.

Abstract: A comparing circuit which suppresses an electric power consumption and promptly traces a DC offset when shifting to a receiving mode. The comparing circuit which needs to trace a DC offset potential is provided with means for enabling power down control functions of a reference voltage generating part and a voltage comparing part on the output side of the part to be independently controlled. In the receiving mode of an apparatus in which the comparing circuit is installed, the reference voltage generating part and voltage comparing part are made operative. In a transmitting mode of the apparatus, only the reference voltage generating part is made operative. In a pause mode of the apparatus, the reference voltage generating part and voltage comparing part are set in a power down state.

Abstract: A comparing circuit which suppresses an electric power consumption and promptly traces a DC offset when shifting to a receiving mode. The comparing circuit which needs to trace a DC offset potential is provided with means for enabling power down control functions of a reference voltage generating part and a voltage comparing part on the output side of the part to be independently controlled. In the receiving mode of an apparatus in which the comparing circuit is installed, the reference voltage generating part and voltage comparing part are made operative. In a transmitting mode of the apparatus, only the reference voltage generating part is made operative. In a pause mode of the apparatus, the reference voltage generating part and voltage comparing part are set in a power down state.

Abstract: A tuning circuit includes an oscillator that receives an oscillating input signal and a control signal, and generates an oscillating output signal. The control signal is obtained from a frequency control circuit that compares the phases of the oscillating output signal and a reference signal. The control signal controls the transconductance of a transconductance element in the oscillator, thereby controlling the oscillator output frequency. The oscillating input signal is obtained from an amplitude control circuit that detects an amplitude limit of the oscillator output. The oscillator output amplitude is responsive to the oscillating input signal. Frequency control and amplitude control in this tuning circuit are mutually independent, so their respective control loops remain stable under all frequency and amplitude combinations.

Abstract: There is provided an electronic inductance circuit having a transistor, a first resistor, a second resistor, a capacitor and a first current source. The main current path of the transistor and the first resistor are connected in series to form a first serial circuit between an input terminal and an output terminal. The second resistor and the capacitor are connected in series to form a second serial circuit between the input and output terminals, thus forming a parallel circuit of the first and second serial circuits. The connection point between the second resistor and the capacitor is coupled to the control terminal of the transistor. The connection point is connected to the first current source for determining the operating point of the transistor.