Abstract: In bit phase synchronizing circuitry, received data with an unknown phase and triphase clocks output from a reset VCO (Voltage Controlled Oscillator) are input to a timing decision circuit. If preselected one of the triphase clocks and the received data have an adequate relation, the decision circuit causes the current clock phase to be maintained. If otherwise, the decision circuit determines whether the current clock phase should be advanced or retarded. The resulting decision signal output from the decision circuit is fed to a selector controller. The decision circuit latches the received data with the preselected one of the triphase clocks and outputs them together with the clock used for latching. A phase controller causes the reset VCO to selectively operate in a phase shift mode or in a multiplication PLL (Phase Locked Loop) mode. The circuitry is capable of setting up bit phase synchronization stably and rapidly with a simple configuration without regard to the phase of the received data.

Abstract: A bit-phase aligning circuit includes a bit-phase adjusting circuit and a synchronizing pattern detection circuit. The bit-phase adjusting circuit adjusts a phase difference between a data signal and a clock signal by adjusting a delay amount of the data signal based on a determination result signal from the synchronizing pattern detection circuit. In the synchronizing pattern detection circuit, the data signal is sampled using the clock signal so as to detect a synchronizing pattern inserted in the data signal. When the synchronizing pattern is detected, the synchronizing pattern detection circuit determines that a phase relationship between the data signal and the clock signal is proper. On the other hand, when not detected, the synchronizing pattern detection circuit determines the phase relationship therebetween to be improper. This determination result signal is fed to the bit-phase adjusting circuit where the phase difference between the data signal and the clock signal is adjusted.

Abstract: A PLL circuit suitable for fabrication into an integrated circuit includes: a first phase comparator for determining a phase difference between an input signal and a first feedback signal to produce a first phase difference signal in rsponse to the phase difference; a first loop filter for removing a high frequency constituent from the first phase difference signal; a first variable frequency oscillator which oscillates at a frequency which varies in response to an output of the first loop filter to produce the first feedback signal; a second phase comparator for determining a phase difference between a reference signal and a second feedback signal to produce a second phase difference signal in response to the phase difference; a second loop filter for removing a high frequency constituent from the second phase difference signal; a second variable frequency oscillator having substantially the same characteristics as those of the first variable frequency, oscillator which oscillates at a frequency which varies

Abstract: The present invention describes a low power consumption type subscriber line interface circuit (SLIC). The SLIC described in the present invention includes a first pair of potential detectors each of which detects the potential difference between each corresponding subscriber line and a first predetermined value, a second pair of potential difference detectors each of which detects a potential difference between each corresponding subscriber line and a second predetermined value, a pair of signal adder circuits each of which sums output signals from one of the first potential difference detectors and one of the second potential difference detectors, and a pair of amplifiers each of which amplifies each output signal from each signal summing circuit and returns a direct current to the each of corresponding subscriber lines.

Abstract: A current source type current output circuit for applying to a load a current which is proportional to an input includes an amplifier of the type receiving a current and producing a voltage, and a feedback circuit for feeding back an output of the amplifier to an input terminal of the amplifier. The feedback circuit is made up of a first, a second, and a third current mirror circuit, and a first, a second, and a third resistor. An output terminal of the amplifier is connected to an input terminal of the second current mirror circuit via the third resistor and to an input terminal of the first current mirror circuit via a series connection of the first and second resistors. The load is connected to the intermediate point of the serial connection of the first and second resistors. An output terminal of the second current mirror circuit is connected to an input terminal of the third current mirror circuit.