Abstract: A video information analysis system that objectively and instantaneously evaluates a value of broadcasting information broadcasted on television or video information distributed and provided through the Internet to make it possible to examine influences including an economic influence of the television related broadcasting information or the video information provided through the Internet on a company, an association, an individual, a commodity, a service, a brand and the like, and compares the pieces of information with various economic indicators to make it possible to consider correlation between the video information and the evaluations of the company, the association, and the like.

Abstract: A video information analysis system that objectively and instantaneously evaluates a value of broadcasting information broadcasted on television or video information distributed and provided through the Internet to make it possible to examine influences including an economic influence of the television related broadcasting information or the video information provided through the Internet on a company, an association, an individual, a commodity, a service, a brand and the like, and compares the pieces of information with various economic indicators to make it possible to consider correlation between the video information and the evaluations of the company, the association, and the like.

Abstract: A colored light generating element can be configured to, while in an active state, pulse between an off state and an on state. A substantially constant offset voltage or current can be applied to the colored light generating element during a predetermined time interval when the light generating element is in the off state so as to cause the colored light generating element to emit, during the off state, some amount of light greater than a minimum amount of light that the light generating element is capable of generating while part of an active system. In some implementations, two or more offset voltages or currents can be applied. Implementations may include a preprocessor configured to receive an image signal and optimize color saturation of the image signal, such as by limiting and non-linearly increasing color saturation. Implementations may include multiple colored light generating elements.

Abstract: A method for improving brightness of projected images from an LED projector employing a plurality of LEDs of different colors by determining, from a histogram of a frame of an image to be projected, an effective maximum saturation. A plurality of main channels and a plurality of subchannels are created, one main channel and at least one subchannel for each color LED. Then the amplitude of the main channel and a subchannel for each color are determined based upon the effective maximum saturation of the frame of the image, followed by using the main channel and the at least one subchannel for a color to drive an LED of that color to generate the image.

Abstract: Methods, systems, and apparatus, including computer program products, for reducing artifacts in a color sequential display system. A frame of a digital image is displayed by receiving frame data, determining dither patterns, applying the dither patterns to the data, and displaying the dithered data. Each pixel of a frame of a digital image is displayed by receiving pixel data, grouping the pixel data for the color channels of the image into a plurality of sub-groups of pixel data; and displaying the pixel according to a sequence that separates each pair of sub-groups for a color channel by a sub-group for another color channel. Modified pixel data can be generated by replacing parent bits in the pixel data with corresponding pluralities of divided child bits, where all the child bits for a given parent bit have a divided weight that adds up to the parent bit's weight.

Abstract: Methods, systems, and apparatus, including computer program products, for reducing artifacts in a color sequential display system. A frame of a digital image is displayed by receiving frame data, determining dither patterns, applying the dither patterns to the data, and displaying the dithered data. Each pixel of a frame of a digital image is displayed by receiving pixel data, grouping the pixel data for the color channels of the image into a plurality of sub-groups of pixel data; and displaying the pixel according to a sequence that separates each pair of sub-groups for a color channel by a sub-group for another color channel. Modified pixel data can be generated by replacing parent bits in the pixel data with corresponding pluralities of divided child bits, where all the child bits for a given parent bit have a divided weight that adds up to the parent bit's weight.

Abstract: A colored light generating element can be configured to, while in an active state, pulse between an off state and an on state. A substantially constant offset voltage or current can be applied to the colored light generating element during a predetermined time interval when the light generating element is in the off state so as to cause the colored light generating element to emit, during the off state, some amount of light greater than a minimum amount of light that the light generating element is capable of generating while part of an active system. In some implementations, two or more offset voltages or currents can be applied. Implementations may include a preprocessor configured to receive an image signal and optimize color saturation of the image signal, such as by limiting and non-linearly increasing color saturation. Implementations may include multiple colored light generating elements.

Abstract: A method and system are provided for managing digital color for a display device having a display screen. Aspects the exemplary embodiments include receiving input display data comprising digital pixel data, wherein the data for each pixel represents 2D differential color space having X, Y coordinate values; remapping at least a portion of the coordinate values of the input display data locally in coordinates of the differential color space by reading from a memory of the display device color correction data that is configured to correct color errors of the display screen, wherein the color correction data is also represented in the differential color space, but the color correction data is only stored for a subset of X, Y coordinate values comprising the differential color space; interpolating the correction data read from the memory to generate remapped display data; and outputting the remapped display data for subsequent display.

Abstract: A method and system for cross color elimination is disclosed in processing of a component video signal comprising component luminance and chrominance information. Aspects of the exemplary embodiments include using separated luminance and chrominance information for each pixel in a current frame, getting absolute distance values between C=a current frame pixel color, P=a previous frame pixel color, H=a high frequency color of the previous frame, and O=a center of a color space; comparing each absolute distance value with a predetermined threshold, wherein if any of the absolute distance values exceed the predetermined threshold, then the pixel is a cross color pixel; and for each cross color pixel, replacing a current frame pixel color with a high frequency average pixel color.

Abstract: A method and system are provided for correcting non-uniformity of a display device having a display screen comprising a pixel matrix. Aspects the exemplary embodiment include in response to receiving display data for display, reading from a memory of the display device compensation data stored for a subset of pixel locations on the display screen, the compensation data configured to correct non-uniformity characteristics of the display screen; interpolating the compensation data to generate uniformity correction data; overlaying the display data with the uniformity correction data to produce uniformity corrected display data; and outputting the uniformity corrected display data for subsequent display.

Abstract: A method and system are provided for performing gamma correction on display data. Aspects the exemplary embodiment include using at least a portion of the display data to fetch in parallel from a table memory a gamma correction data value stored at an odd address and a gamma correction data value stored at an even address; detecting when the display data comprises a low address; and in response to detecting that the display data comprises a low address, performing a right shift on the gamma correction data values, thereby decreasing the values of the gamma correction data prior to performing interpolation on the gamma compensation data values.

Abstract: A frame rate controller method and system are provided.

Abstract: A configuration/apparatus to drive emphasized data to an LCD screen, including enhancing frame difference data with compensation and enhancement factors. These factors can consider a backlight phase input from a variable backlight control system.

Abstract: A graphics controller for a System-On-a-Chip (SOC) used with a battery-powered device allows for reduced-power display modes. The microprocessor writes to a frame buffer that is a single, contiguous address block in virtual memory. A memory management unit (MMU) translates frame-buffer address to multiple physical blocks. The graphics controller fetches pixels from the multiple physical blocks, including a block in an on-chip memory and a block in an external memory. In a low-power mode, pixels are only fetched from the lower-power on-chip memory and not the higher-power external memory. A smaller display window is defined and pixels outside the window are replaced by dummy data,.eliminating external-memory fetches. The smaller display window falls within the first block in the on-chip memory. Status and other information can be displayed in the smaller display window during stand-by modes, while a full-screen of data is displayed for full-power modes.

Abstract: A display subsystem supports both normal mode and portrait mode displays. In normal mode, the scan starts at the upper left comer of the display. In portrait mode, the scan starts at the lower left comer of the display. The display subsystem includes a dual mapped display memory having a normal mode display area and a portrait mode display area. The portrait mode display area is defined by X-ofst(Virtual) and Y-ofst. X-ofst(Virtual) is a power of two that is greater than the real X-ofst supported by the display in portrait mode. Address requests from the CPU or software use high order bits to specify whether the address is in the normal or portrait mode display area. In addition, address requests to the portrait mode display area use the address space defined by X-ofst(Virtual) and Y-ofst. When the address request specifies the portrait mode display area, the address of the request is translated to account for the different mode of the display.

Abstract: A flat-panel display controller generates signals to cause display of images on TFT and STN type flat-panel displays. The display controller includes dither logic and frame rate control logic. The dither logic performs dynamic and distributed dithering on pixel data to generate smooth 16 gray-shade images on the display. The dynamic and distributed dithering capabilities are programmable. Dynamic dithering is programmable to specify, two-phase, four-phase or eight-phase mixes to generate signals for use by TFT and STN type flat-panel displays. The frame rate control logic is responsive to the dither logic and performs frame rate control on the dithered signals using stored values indicative of average pixel luminescence to generate 256 gray-shades.

Abstract: A flat-panel display controller generates signals to cause display of images on TFT and STN type flat-panel displays. The display controller includes dither logic and frame rate control logic. The dither logic performs dynamic and distributed dithering on pixel data to generate smooth 16 gray-shade images on the display. The dynamic and distributed dithering capabilities are programmable. Dynamic dithering is programmable to specify, two-phase, four-phase or eight-phase mixes to generate signals for use by TFT and STN type flat-panel displays. The frame rate control logic is responsive to the dither logic and performs frame rate control on the dithered signals using stored values indicative of average pixel luminescence to generate 256 gray-shades.

Abstract: A video deinterlacing system receives interlaced video data at a non-deterministic rate and generates non-interlaced data as a function of the interlaced video data. The system includes processing units, some of which require clocking rates that differ from clocking rates required by other processing units. A timing generator responds to a base clock and to a data valid signal, that indicates arrival of a portion of the interlaced video data, to cause generation of a plurality of enable signals. Each of the enable signals operate to enable a corresponding one of the clocking rates required by the processing units. Video capture can be performed by causing capture of video frames that meet or exceed a specified quality level. The quality of the captured, still image, video can be improved by disabling certain enhancement functions performed to improve moving video images.

Abstract: A graphics controller for a System-On-a-Chip (SOC) used with a battery-powered device allows for reduced-power display modes. The microprocessor writes to a frame buffer that is a single, contiguous address block in virtual memory. A memory management unit (MMU) translates frame-buffer address to multiple physical blocks. The graphics controller fetches pixels from the multiple physical blocks, including a block in an on-chip memory and a block in an external memory. In a low-power mode, pixels are only fetched from the lower-power on-chip memory and not the higher-power external memory. A smaller display window is defined and pixels outside the window are replaced by dummy data, .eliminating external-memory fetches. The smaller display window falls within the first block in the on-chip memory. Status and other information can be displayed in the smaller display window during stand-by modes, while a full-screen of data is displayed for full-power modes.

Abstract: A graphics controller for a System-On-a-Chip (SOC) used with a battery-powered device allows for reduced-power display modes. The microprocessor writes to a frame buffer that is a single, contiguous address block in virtual memory. A memory management unit (MMU) translates frame-buffer address to multiple physical blocks. The graphics controller fetches pixels from the multiple physical blocks, including a block in an on-chip memory and a block in an external memory. In a low-power mode, pixels are only fetched from the lower-power on-chip memory and not the higher-power external memory. A smaller display window is defined and pixels outside the window are replaced by dummy data, .eliminating external-memory fetches. The smaller display window falls within the first block in the on-chip memory. Status and other information can be displayed in the smaller display window during stand-by modes, while a full-screen of data is displayed for full-power modes.