Abstract: Frame-rate control electronic provides gray-scale display control algorithm for STN LCD devices and constant brightness display with randomized pattern algorithm. Even distribution control of phase number reduces screen flicker and stabilizes gray-scale display. Randomized and scrambled phase number control eliminates screen beating artifacts, such as when image includes dither and checker patterns. Programmable parameters, such as tuning value, phase number matrices, and frame offset numbers, may be chosen flexibly to optimize conditions to certain display.

Abstract: A computer graphics subsystem according to a preferred embodiment of the present invention has a video digital signal processor (VDSP) that normally requires a plurality of discrete field and line memories, but, instead, is adapted to use multiple-port ring buffers (MPRBs) in an internal memory and/or an external display memory. Each MPRB comprises a plurality of addressable storage location holding video data and linked in a logical ring configuration. In addition, each MPRB has at least three ports, selected from write ports for writing to the addresses of the storage locations and read ports for reading from the addresses. Each read port in the MPRB is disposed a certain distance, or number of storage locations, behind a write port. This distance defines the size of the memory emulated by the MPRB. By positioning multiple read ports at different distances from the write ports, a single MPRB can emulate several different memories of different sizes.

Abstract: A video deinterlacing system receives interlaced video data at a non-deterministic rate and generates non-interlaced data as a function of the interlaced video data. The system includes processing units, some of which require clocking rates that differ from clocking rates required by other processing units. A timing generator responds to a base clock and to a data valid signal, that indicates arrival of a portion of the interlaced video data, to cause generation of a plurality of enable signals. Each of the enable signals operate to enable a corresponding one of the clocking rates required by the processing units. Video capture can be performed by causing capture of video frames that meet or exceed a specified quality level. The quality of the captured, still image, video can be improved by disabling certain enhancement functions performed to improve moving video images.

Abstract: A flat-panel display controller generates signals to cause display of images on TFT and STN type flat-panel displays. The display controller includes dither logic and frame rate control logic. The dither logic performs dynamic and distributed dithering on pixel data to generate smooth 16 gray-shade images on the display. The dynamic and distributed dithering capabilities are programmable. Dynamic dithering is programmable to specify, two-phase, four-phase or eight-phase mixes.to generate signals for use by TFT and STN type flat-panel displays. The frame rate control logic is responsive to the dither logic and performs frame rate control on the dithered signals using stored values indicative of average pixel luminescence to generate 256 gray-shades.

Abstract: A computer graphics subsystem according to a preferred embodiment of the present invention has a video digital signal processor (VDSP) that normally requires a plurality of discrete field and line memories, but, instead, is adapted to use multiple-port ring buffers (MPRBs) in an internal memory and/or an external display memory. Each MPRB comprises a plurality of addressable storage location holding video data and linked in a logical ring configuration. In addition, each MPRB has at least three ports, selected from write ports for writing to the addresses of the storage locations and read ports for reading from the addresses. Each read port in the MPRB is disposed a certain distance, or number of storage locations, behind a write port. This distance defines the size of the memory emulated by the MPRB. By positioning multiple read ports at different distances from the write ports, a single MPRB can emulate several different memories of different sizes.

Abstract: A video display control system displays a multicolor animation pattern on a screen of a video display unit. The video display control system is mainly constructed by a video RAM (VRAM) and a video display processor (VDP). The VRAM stores animation pattern data, display position data and at least two color data. The VDP reads these data and makes an animation pattern image displayed in at least two colors at a display position on the screen. The animation pattern image, two colors and display position are determined by the animation pattern data, two color data and display position data. In another video display control system, the VRAM stores at least two sets of animation pattern data, display position data and color data. When displaying two animation patterns, the VDP effects a logical operation on the two color data with respect to the overlapping portion of the two patterns and makes the overlapping portion displayed in a new color corresponding to the operation result.

Abstract: A dynamic random access memory (DRAM) circuit operates in burst mode when a row address strobe (RAS) signal is applied while an output enable/burst enable signal is also applied thereto. During burst mode, a column address strobe (CAS) signal is toggled to access digital data from sequential column addresses within a given row.

Abstract: A character display apparatus comprises at least a memory for storing a character code designating a desirable character and attribute data designating an attribute thereof as one pair of data; a first character generator for pre-storing font data corresponding to English characters and figures; a second character generator for pre-storing font data corresponding to Chinese characters; a judgment portion and a control portion. The judgment portion judges whether one character is designated by one character code or two or more character codes which are read from the memory in accordance with scanning of a display screen. Based on the judgment result of this judgment portion, character reading operation of the control portion is controlled.

Abstract: A memory device utilized for an image display apparatus, such as a dual port memory. The memory device provides a serial port for performing a serial-access with a display controller and a random port for performing a random-access with a CPU. Such memory device includes memory cell arrays of M rows and N columns, one couple of data registers and pointers. The data stored in one row within the memory cell arrays are divided into data of K columns and another data of N-K columns. When the display controller performs the serial-access, one of the above two data registers can be alternatively used for serially inputting or outputting the data while the another data are transferred between the memory cell arrays and another data register. Or the data can be transferred between the memory cell arrays and both of two data registers. In this case, the serial input or output positions for determining the start addresses are assigned by the pointers.

Abstract: A method for generating display patterns using a display memory which stores one bit of data for each pixel of a display apparatus. The stored data represents an outline of a display pattern. The stored data is consecutively read to generate dot data corresponding to the pattern being displayed. Character data corresponding to a current display pixel is also read from a display memory. Then buffer data which relates to a current scan line and the scan line directly above are read from a line buffer. Dot data is generated by performing logical computations on the current pixel data and line buffer data relating to the scan line. The dot data is then written into the line buffer for display.

Abstract: A display apparatus consists of a display memory (VRAM), a data modifier circuit and a display unit at least. The display unit, such as a CRT display unit, has a plurality of display dots which include red, green and blue color dots. The display memory must be cleaned at a primary stage and thereafter a plurality of display codes corresponding to only display dots on the outlines of the color image must be written into the display memory. The display codes are converted into display data which indicate red, green and blue color components. The display codes are successively read out from the display memory and supplied to the data modifier circuit wherein the display data are modified so as to compensate the display data which are not written into the display memory. The display unit displays the image corresponding to the modified display data on the screen thereof.

Abstract: A memory system is provided with two data buffers, respectively, in the row and column directions of a memory array. The system is capable of operating either one of the two data buffers as input/output buffers in accordance with reading or writing operations on the contents of the memory array. Outputs from the memory array are inverted to form an inverted array. All bits along respective columns of the array are ANDed together to obtain an ANDed bit value for each column of the inverted array.

Abstract: A memory storage and accessing device is constituted by a plurality of plane memories. Memory elements are arranged in each plane memory two-dimensionally, and a plurality of image data are stored in a word direction in each plane memory. In addition, plural plane memories are disposed in a pixel direction. Hence, plural image data are stored two-dimensionally in word and pixel directions. The memory device is constituted such that a port connected by a word data bus and another port connected by a pixel data bus are provided therein. Due to these two ports, it is possible to perform an independent access so as to independently read out and write in word data and pixel data. The memory storage and accessing device is capable of masking bits of data and memory units, using both static and dynamic masks. In the static mask, mask data are applied all at once in one memory cycle, or the mask data are supplied to the memory device at plural times in one memory cycle.

Abstract: A display control circuit system is disclosed which, while maintaining the compatibility of software perfectly, can realize various specifications of the software, provides for a gradation display in an LCD display to realize substantially the same level of access as in a CRT display, permits a configuration control, and, when one or more bits are expanded in the conventional software, can protect the function-expanded bit(s). The display control system includes a mode selector to select either a mode for controlling the display of CRT or a mode for controlling the display of LCD, a controller for controlling the CRT display, and a controller for controlling the LCD display control.

Abstract: A display control circuit system is disclosed which, while maintaining the compatibility of software perfectly, can realize various specifications of the software, provides for a gradation display in an LCD display to realize substantially the same level of access as in a CRT display, permits a configuration control, and, when one or more bits are expanded in the conventional software, can protect the function-expanded bit(s). The display control system includes a mode selector to select either a mode for controlling the display of CRT or a mode for controlling the display of LCD, a controller for controlling the CRT display control, and a controller for controlling the LCD display control.

Abstract: A display apparatus consists of a display memory (VRAM), a data modifier circuit and a display unit at least. The display unit, such as a CRT display unit, has a plurality of display dots which include red, green and blue color dots. The display memory must be cleared at a primary stage and thereafter a plurality of display codes corresponding to only display dots on the outlines of the color image must be written into the display memory. The display codes are converted into display data which indicate red, green and blue color components. The display codes are successively read out from the display memory and supplied to the data modifier circuit wherein the display data are modified so as to compensate the display data which are not written into the display memory. The display unit displays the image corresponding to the modified display data on the screen thereof.

Abstract: A display control apparatus is provided in which the moving image of an object is successively compounded with a color picture image from an external source, so as to obtain a compounded image in which the resulting image of the object appears to be moving with respect to the color picture image. The display control apparatus of the present invention includes a register unit for storing color range selecting data therein and circuitry for selecting one of first color image data corresponding to signals which are supplied from an external device, e.g. television camera, and second color image data read from a video memory, e.g. a video random access memory (VRAM). Using data comparison circuitry, the value of color image data selected by the selection circuitry, is compared with the value of the color range selecting data stored in the register unit. Based on the comparison result of the comparator circuitry, either the first color image data or second color image data is selected using a data selector.

Abstract: A video display control system is capable of moving a part of a still image from a first display area to a second display area on a screen. The video display control system includes a memory composed of a plurality of memory locations for storing a plurality of display data representative of images of display elements on the screen. First and second registers retain first and second area data representative of the first and second display areas, and an address data generator generates from these area data first and second address data, the first address data indicating memory locations which store display data corresponding to the first display area, the second address data indicating second memory locations which store display data corresponding to the second display area.

Abstract: An image data processing system operates so that foreground color codes are held in a foreground register, background color codes are held in a background register, and the foreground or background color codes are selectively output by a selector according to the patterns of the pattern data or character fonts to be extended to color codes. Accordingly the pattern data or character font patterns can be extended quickly to the foreground or background color codes.Also, to extend the same pattern data repetitively and quickly to the foreground or background color codes, a rotator or selector is used to enable the pattern data to be used repetitively, and according to the output value thereof the foreground or background register is selected.

Abstract: A display control system has a digital interface therein. When software using a color display is executed and displayed in a monochrome monitor, this system is responsive to color code information to arbitrarily select either a hatching pattern conversion or a grey scale display according to application software or the like. The system can thus discriminate the display contents thereof.In a color monitor that permits input of a plurality of digital signals, the display control system can convert a given piece of color code information into digital video signals according to frames and display positions in a given area of a display screen for display of natural colors.