Abstract: A display control apparatus has a memory for storing luminance data corresponding to a plurality of color elements for color display, the luminance data being used as display data of dots to be displayed at a raster scan type display unit, a circuit for reading out the luminance data corresponding to the respective color elements of given dots for dot display at the display unit, and a video signal converter for enabling/disabling at least one-dot display intervals a binary video signal which is to be transmitted to the display unit and corresponds to a color element when specific luminance data of this color element read out from the memory by the readout circuit has a given level for an interval corresponding to at least two dots along a raster direction, and for transmitting the luminance data to the display unit in accordance with the enable/disabled state of the binary video signal.

Abstract: A video display controller is provided with a color palette circuit which is capable of converting, at a high conversion rate, color codes read from a VRAM (video RAM) into RGB color data to be supplied to a CRT display unit. The color palette circuit comprises a plurality of color data registers each storing one RGB color data and is supplied with a timing signal synchronized with the display timing of display elements on the CRT display screen. Each color code data including at least two color codes and read from an address of the VRAM is first supplied to a selection circuit which includes at least two decoders. Each decoder decodes the corresponding color codes to generate a selection signal which enables one of the color data registers to output the RGB color data contained therein.

Abstract: A video display processor (VDP) for use with a central processing unit, a video RAM (VRAM) and a video display unit is capable of writing video image data supplied from an external video device such as a television set into the VRAM. The VDP comprises a first input terminal for receiving the external video image data and a second input terminal for receiving horizontal and vertical synchronization signals from the external video device. The VDP generates address data in accordance with the horizontal and vertical synchronization signals and supplies the address data to the VRAM when processing of the external video image data is designated. The VDP also supplies the received external video image data to the VRAM thereby to write the external video image data into addresses of the VRAM designated by the address data.

Abstract: A video display controller which can display foregrounds as well as backgrounds of display patterns on a screen of a video display unit in a plurality of colors. The video display controller comprises a plurality of color information registers, in each of which a pair of color code data representative of foreground and background colors of one display pattern are stored. A memory is provided for storing a plurality of pattern data, a plurality of pattern name data each designating one of the display patterns to be displayed on a respective one of display portions of the screen, and a plurality of color selection data each corresponding to a respective one of the display portions. A sequence controller sequentially reads the pattern data designated by the pattern name data and the color selection data in accordance with synchronization signals.

Abstract: A video display control system comprises a video display processor (VDP) which is capable of accessing to a video RAM (VRAM) at an extremely high-speed. The VRAM used in this system comprises first and second dynamic RAMs each having an address input terminal to which row address data and column address data are supplied, a row address strobe input terminal, a column address strobe input terminal, and a data input/output terminal. The row address data is latched at the leading edge of a row address strobe signal applied to the row address strobe input terminal, while the column address data is latched at the leading edge of a column address strobe signal applied to the column address strobe input terminal. An access to an address of each dynamic RAM is established when both of the row and column address data are latched. The VDP comprises a VRAM interface for controlling an access to the first and second dynamic RAMs which is connected to the RAMs through a common address bus.

Abstract: A keyboard unit control system having a port which includes a block selection register for specifying one of a plurality of blocks of scanning lines and a scanning data selection register for specifying one of the scanning lines of the corresponding block. The scanning data and block data are supplied to a keyboard unit through the scan line selecting logic. When the operator depresses a key on the keyboard unit, the key is detected by an interrupt detector and a detection signal is supplied to a CPU. The CPU first scans the blocks and then scans the scanning lines in the corresponding block.

Abstract: A data transfer system in which a data entry system is converted from manual operation to automatic reading in a computer system, thereby to save time in the inputting of data into the computer system. The data entry system includes a main processor having a central processing unit (CPU) and a keyboard unit including a microprocessor. Provision of the microprocessor at the keyboard enables physical separation of the keyboard unit from the CPU by means of only a single bi-directional cable. The CPU periodically sends polling data in serial data format via the bi-directional cable to the keyboard microprocessor, which then controls a keyboard matrix scanning operation in performing the commands represented by the polling data. The microprocessor then controls serial transmission of keyboard data to the CPU via the bi-directional cable. Thus the data transfer system is suitable for high performance data transfer between the CPU of the main processor and the microprocessor of the keyboard unit.

Abstract: A memory multiplex address system which increases the effective size of the address space of a processor. A first memory from which data is normally read and a second memory into which data is normally written are assigned the same address space. A read/write signal is employed to select the appropriate memory. In a second mode, data may be written into the first memory and read from the second memory. Alternatively, any conceivable address space layout may be employed in the second mode.

Abstract: An input data synchronizing circuit of the invention has a synchronous control counter. Part of count value of the synchronous control counter is supplied to a count register. The count register accesses a parameter ROM utilizing, as part of an address, a count value (phase status) during the input of current data and a count value (phase status) during input of immediately preceding data. The parameter ROM outputs a correction value as an initial value for the synchronous control counter so that the synchronous control counter would output a WINDOW signal synchronous with the input data near the center of the pulse width of the WINDOW signal. The circuit of the invention further includes a rotation correction register which holds stationary time shift information serially input by the rotational errors of the floppy disk drives and which outputs the information to the parameter ROM as part of the address.

Abstract: An error display circuit in a data processing device containing an independent processor circuit is set by an initializing signal generated when a power source is turned on and reset by the operation of the processor circuit when the initializing signal is removed. By this means the fact that the processor circuit can operate normally at a level above a definite degree can be affirmed by the state of the display circuit.

Abstract: A dual data processing system comprising a first data processing unit having a first control unit and a first logic switching circuit; a second control unit having a second logic switching circuit; a pair of switch circuits coupled to the first and second logic switching circuits, respectively; adapter buffers to be coupled selectively to the first and second control units according to the operation of the switch circuits; a first power source for supplying electric power to the first control unit and the adapter buffers coupled thereto; and a second power source for supplying electric power to the second control unit and the adapter buffers coupled thereto. The switch circuits are operated to connect the adapter buffers selectively to the first and second control units so that load balance is kept between the first and second control units.