Abstract: A wiring sheet includes one or more carbon wires each of which is one of a signal line and a power supply line, and which are conductors including carbon as a main material and have flexibility; and an insulation sheet that encloses substantially an entirety of the one or more carbon wires, includes an electrical insulator as a main material, and has flexibility.

Abstract: An object to provide an electric device easy to manufacture, extensible and of high quality. The electric device comprises a plurality of module boards 51, the module boards 51 piled up on one another, each of the module boards 51 provided with an electrode 53 on its surface, the electrodes 53 on the piled-up module boards 51 generally positioned along a vertical straight line; and a connector 11 connecting the module boards 51, the connector 11 including a body portion 21, the body portion 21 electrically connecting the electrodes 53 positioned along the vertical straight line, and a holder 12 holding the body portion 21, the holder 12 including a board engagement portion and a holder connecting portion, the board engagement portion engaging with the module board 51 so that the connector 11 is mounted on the module board 51, and the holder connecting portion engaging with another holder connecting portion so that the connector 11 is coupled to another vertically adjacent connector 11.

Abstract: An object to provide an electric device easy to manufacture, extensible and of high quality. The electric device comprises a plurality of module boards 51, the module boards 51 piled up on one another, each of the module boards 51 provided with an electrode 53 on its surface, the electrodes 53 on the piled-up module boards 51 generally positioned along a vertical straight line; and a connector 11 connecting the module boards 51, the connector 11 including a body portion 21, the body portion 21 electrically connecting the electrodes 53 positioned along the vertical straight line, and a holder 12 holding the body portion 21, the holder 12 including a board engagement portion and a holder connecting portion, the board engagement portion engaging with the module board 51 so that the connector 11 is mounted on the module board 51, and the holder connecting portion engaging with another holder connecting portion so that the connector 11 is coupled to another vertically adjacent connector 11.

Abstract: A wiring sheet includes one or more carbon wires each of which is one of a signal line and a power supply line, and which are conductors including carbon as a main material and have flexibility; and an insulation sheet that encloses substantially an entirety of the one or more carbon wires, includes an electrical insulator as a main material, and has flexibility.

Abstract: A signal detection device includes: multiple electrodes that are arranged to come into contact with a subject that generates a signal; an electrode signal selection unit that alternatively selects one signal from signals on the multiple electrodes based on a selection signal; an amplification unit that amplifies the signal that is selected by the electrode signal selection unit; and a flexible substrate on which the multiple electrodes, the selection unit, and the amplification unit are formed, in which the amplification unit is formed on the substrate to form a laminated structure together with the multiple electrodes and the selection unit.

Abstract: For example, an averaging circuit includes first to third capacitors and a controller. The controller causes a first first-stage average voltage to be applied to a first capacitor, the first first-stage average voltage being an average of a first voltage applied to the first capacitor and a second voltage applied to a second capacitor, causes a second first-stage average voltage to be applied to the second capacitor, the second first-stage average voltage being an average of a third voltage applied to the second capacitor and a fourth voltage applied to a third capacitor, and causes a first second-stage average voltage to be applied to the first capacitor, the first second-stage average voltage being an average of the first and second first-stage average voltages applied to the first and second capacitors.

Abstract: According to one embodiment, an oscillator circuit includes a resonant circuit and first and second negative-resistance circuits. Each of the first and second negative-resistance circuits includes a first power-supply terminal, a second power-supply terminal, an input terminal and an output terminal. The first and second negative-resistance circuits are connected in series between a first power supply and a second power supply at the first and second power-supply terminals, and connected parallel to the resonance circuit at the input and output terminals.

Abstract: For example, an averaging circuit includes first to third capacitors and a controller. The controller causes a first first-stage average voltage to be applied to a first capacitor, the first first-stage average voltage being an average of a first voltage applied to the first capacitor and a second voltage applied to a second capacitor, causes a second first-stage average voltage to be applied to the second capacitor, the second first-stage average voltage being an average of a third voltage applied to the second capacitor and a fourth voltage applied to a third capacitor, and causes a first second-stage average voltage to be applied to the first capacitor, the first second-stage average voltage being an average of the first and second first-stage average voltages applied to the first and second capacitors.

Abstract: According to one embodiment, an oscillator circuit includes a resonant circuit and first and second negative-resistance circuits. Each of the first and second negative-resistance circuits includes a first power-supply terminal, a second power-supply terminal, an input terminal and an output terminal. The first and second negative-resistance circuits are connected in series between a first power supply and a second power supply at the first and second power-supply terminals, and connected parallel to the resonance circuit at the input and output terminals.

Abstract: A clock generation circuit 10 includes a resonant reactor connected with a half voltage supply point TV1, a resonant capacitor CL connected between a ground voltage supply point TVss and an output terminal TVout, a transistor MPconnected between the resonant reactor Lr and the resonant capacitor CL, and a transistor MN1 connected with the output terminal TVout. In this configuration, signals in a wide range of frequencies can be output with low power consumption by adjusting the time when a clock signal ?1 applied to the gates of the transistors MP1 and MN1 is high.

Abstract: A signal detection device includes: multiple electrodes that are arranged to come into contact with a subject that generates a signal; an electrode signal selection unit that alternatively selects one signal from signals on the multiple electrodes based on a selection signal; an amplification unit that amplifies the signal that is selected by the electrode signal selection unit; and a flexible substrate on which the multiple electrodes, the selection unit, and the amplification unit are formed, in which the amplification unit is formed on the substrate to form a laminated structure together with the multiple electrodes and the selection unit.

Abstract: A booster circuit is configured, such that: in response to a reading request for reading data from a flash memory, when a voltage of an output terminal detected by a voltage detection circuit is not higher than a voltage, an oscillator outputs a control clock signal of predetermined on time and off time to a transistor of a boost converter to perform switching control of the transistor; and when the voltage detection circuit detects that the voltage of the output terminal reaches a voltage, an oscillator outputs a control clock signal of an on time and an off time input from a selection circuit to a transistor of a boost converter to perform switching control of the transistor.

Abstract: In a voltage detecting circuit, a transistor is configured as a P-type MOSFET, and includes a source connected with an input terminal, a gate connected with a ground voltage terminal and a drain connected with an output terminal. A transistor is configured as a P-type MOSFET, and includes a gate and a source connected with the output terminal and a drain connected with the ground terminal. Gate width and gate length of the transistor and gate width and gate length of the transistor are adjusted so that source-drain current flowing between the source and the drain of the transistor becomes equal to source-drain current flowing between the source and the drain of the transistor when the voltage applied to the input terminal is set to be preset trigger voltage. This configuration accomplishes detecting that the input voltage exceeds the trigger voltage with simple configuration.

Abstract: The interposer 30 is disposed on an upper surface of the stacked structure 24 formed by stacking a plurality of a DRAM chip 20 and a plurality of a flash memory chip 22. Thus down-size of an entire device is accomplished. A boost converter having an inductor is used as a voltage boost circuit 40. Thus down-size of the entire device is accomplished.

Abstract: A booster circuit is configured, such that: in response to a reading request for reading data from a flash memory, when a voltage of an output terminal detected by a voltage detection circuit is not higher than a voltage, an oscillator outputs a control clock signal of predetermined on time and off time to a transistor of a boost converter to perform switching control of the transistor; and when the voltage detection circuit detects that the voltage of the output terminal reaches a voltage, an oscillator outputs a control clock signal of an on time and an off time input from a selection circuit to a transistor of a boost converter to perform switching control of the transistor.

Abstract: A clock generation circuit 10 includes a resonant reactor connected with a half voltage supply point TV1, a resonant capacitor CL connected between a ground voltage supply point TVss and an output terminal TVout, a transistor MP1 connected between the resonant reactor Lr and the resonant capacitor CL, and a transistor MN1 connected with the output terminal TVout. In this configuration, signals in a wide range of frequencies can be output with low power consumption by adjusting the time when a clock signal ?1 applied to the gates of the transistors MP1 and MN1 is high.

Abstract: The voltage Vdd is set to be lower than in the normal operation (step S100), then voltage is applied to each of the power-supply voltage applied node Vdd, the ground voltage applied node Vss, the semiconductor substrate and the well so that relative high voltage between the gate of turn-on transistor and the semiconductor substrate or the gate of turn-on transistor and well (steps S110 and S120). This process accomplishes rising of the threshold voltage of the transistor that is turned on, the reduction of the variation in the threshold voltage between a plurality of the transistors of the memory cell including latch circuit, and the improvement of the voltage characteristic of the memory cell.

Abstract: The channel number detecting circuit detects the operation channel number based on the output terminal voltage after falling down when the output terminal voltage falls down during the voltage boosting control, and the switching control circuit generates the control clock signal having the on-time and the off-time adjusted based on the operation channel number and performs the voltage boosting control using generating control clock signal. The voltage boosting control is properly performed based on the operation channel number when the operation channel number increase during performing the voltage boosting control. Thus boosting the power supply voltage up to a second voltage is accomplished.

Abstract: In a voltage detecting circuit, a transistor is configured as a P-type MOSFET, and includes a source connected with an input terminal, a gate connected with a ground voltage terminal and a drain connected with an output terminal. A transistor is configured as a P-type MOSFET, and includes a gate and a source connected with the output terminal and a drain connected with the ground terminal. Gate width and gate length of the transistor and gate width and gate length of the transistor are adjusted so that source-drain current flowing between the source and the drain of the transistor becomes equal to source-drain current flowing between the source and the drain of the transistor when the voltage applied to the input terminal is set to be preset trigger voltage. This configuration accomplishes detecting that the input voltage exceeds the trigger voltage with simple configuration.

Abstract: The voltage Vdd is set to be lower than in the normal operation (step S100), then voltage is applied to each of the power-supply voltage applied node Vdd, the ground voltage applied node Vss, the semiconductor substrate and the well so that relative high voltage between the gate of turn-on transistor and the semiconductor substrate or the gate of turn-on transistor and well (steps S110 and S120). This process accomplishes rising of the threshold voltage of the transistor that is turned on, the reduction of the variation in the threshold voltage between a plurality of the transistors of the memory cell including latch circuit, and the improvement of the voltage characteristic of the memory cell.