Patents by Inventor Takayasu Sakurai

Takayasu Sakurai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10413247
    Abstract: A signal detection device includes: multiple electrodes that are arranged to come into contact with a subject that generates a signal; an electrode signal selection unit that alternatively selects one signal from signals on the multiple electrodes based on a selection signal; an amplification unit that amplifies the signal that is selected by the electrode signal selection unit; and a flexible substrate on which the multiple electrodes, the selection unit, and the amplification unit are formed, in which the amplification unit is formed on the substrate to form a laminated structure together with the multiple electrodes and the selection unit.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: September 17, 2019
    Assignee: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Hiroshi Fuketa, Makoto Takamiya, Takayasu Sakurai, Tsuyoshi Sekitani, Takao Someya
  • Patent number: 10177750
    Abstract: For example, an averaging circuit includes first to third capacitors and a controller. The controller causes a first first-stage average voltage to be applied to a first capacitor, the first first-stage average voltage being an average of a first voltage applied to the first capacitor and a second voltage applied to a second capacitor, causes a second first-stage average voltage to be applied to the second capacitor, the second first-stage average voltage being an average of a third voltage applied to the second capacitor and a fourth voltage applied to a third capacitor, and causes a first second-stage average voltage to be applied to the first capacitor, the first second-stage average voltage being an average of the first and second first-stage average voltages applied to the first and second capacitors.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: January 8, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Sungjun Lee, Makoto Takamiya, Takayasu Sakurai
  • Patent number: 10116261
    Abstract: According to one embodiment, an oscillator circuit includes a resonant circuit and first and second negative-resistance circuits. Each of the first and second negative-resistance circuits includes a first power-supply terminal, a second power-supply terminal, an input terminal and an output terminal. The first and second negative-resistance circuits are connected in series between a first power supply and a second power supply at the first and second power-supply terminals, and connected parallel to the resonance circuit at the input and output terminals.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: October 30, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shunta Iguchi, Makoto Takamiya, Takayasu Sakurai
  • Publication number: 20170230035
    Abstract: For example, an averaging circuit includes first to third capacitors and a controller. The controller causes a first first-stage average voltage to be applied to a first capacitor, the first first-stage average voltage being an average of a first voltage applied to the first capacitor and a second voltage applied to a second capacitor, causes a second first-stage average voltage to be applied to the second capacitor, the second first-stage average voltage being an average of a third voltage applied to the second capacitor and a fourth voltage applied to a third capacitor, and causes a first second-stage average voltage to be applied to the first capacitor, the first second-stage average voltage being an average of the first and second first-stage average voltages applied to the first and second capacitors.
    Type: Application
    Filed: September 12, 2016
    Publication date: August 10, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Sungjun LEE, Makoto TAKAMIYA, Takayasu SAKURAI
  • Publication number: 20170201216
    Abstract: According to one embodiment, an oscillator circuit includes a resonant circuit and first and second negative-resistance circuits. Each of the first and second negative-resistance circuits includes a first power-supply terminal, a second power-supply terminal, an input terminal and an output terminal. The first and second negative-resistance circuits are connected in series between a first power supply and a second power supply at the first and second power-supply terminals, and connected parallel to the resonance circuit at the input and output terminals.
    Type: Application
    Filed: September 2, 2016
    Publication date: July 13, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shunta IGUCHI, Makoto TAKAMIYA, Takayasu SAKURAI
  • Patent number: 9276589
    Abstract: A clock generation circuit 10 includes a resonant reactor connected with a half voltage supply point TV1, a resonant capacitor CL connected between a ground voltage supply point TVss and an output terminal TVout, a transistor MPconnected between the resonant reactor Lr and the resonant capacitor CL, and a transistor MN1 connected with the output terminal TVout. In this configuration, signals in a wide range of frequencies can be output with low power consumption by adjusting the time when a clock signal ?1 applied to the gates of the transistors MP1 and MN1 is high.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: March 1, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Fuketa, Makoto Takamiya, Takayasu Sakurai
  • Publication number: 20160007927
    Abstract: A signal detection device includes: multiple electrodes that are arranged to come into contact with a subject that generates a signal; an electrode signal selection unit that alternatively selects one signal from signals on the multiple electrodes based on a selection signal; an amplification unit that amplifies the signal that is selected by the electrode signal selection unit; and a flexible substrate on which the multiple electrodes, the selection unit, and the amplification unit are formed, in which the amplification unit is formed on the substrate to form a laminated structure together with the multiple electrodes and the selection unit.
    Type: Application
    Filed: February 14, 2014
    Publication date: January 14, 2016
    Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Hiroshi FUKETA, Makoto TAKAMIYA, Takayasu SAKURAI, Tsuyoshi SEKITANI, Takao SOMEYA
  • Patent number: 9036443
    Abstract: A booster circuit is configured, such that: in response to a reading request for reading data from a flash memory, when a voltage of an output terminal detected by a voltage detection circuit is not higher than a voltage, an oscillator outputs a control clock signal of predetermined on time and off time to a transistor of a boost converter to perform switching control of the transistor; and when the voltage detection circuit detects that the voltage of the output terminal reaches a voltage, an oscillator outputs a control clock signal of an on time and an off time input from a selection circuit to a transistor of a boost converter to perform switching control of the transistor.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: May 19, 2015
    Assignee: THE UNIVERSITY OF TOKYO
    Inventors: Ken Takeuchi, Teruyoshi Hatanaka, Koichi Ishida, Tadashi Yasufuku, Makoto Takamiya, Takayasu Sakurai
  • Patent number: 9000751
    Abstract: In a voltage detecting circuit, a transistor is configured as a P-type MOSFET, and includes a source connected with an input terminal, a gate connected with a ground voltage terminal and a drain connected with an output terminal. A transistor is configured as a P-type MOSFET, and includes a gate and a source connected with the output terminal and a drain connected with the ground terminal. Gate width and gate length of the transistor and gate width and gate length of the transistor are adjusted so that source-drain current flowing between the source and the drain of the transistor becomes equal to source-drain current flowing between the source and the drain of the transistor when the voltage applied to the input terminal is set to be preset trigger voltage. This configuration accomplishes detecting that the input voltage exceeds the trigger voltage with simple configuration.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: April 7, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Po-Hung Chen, Makoto Takamiya, Takayasu Sakurai
  • Patent number: 8742838
    Abstract: The interposer 30 is disposed on an upper surface of the stacked structure 24 formed by stacking a plurality of a DRAM chip 20 and a plurality of a flash memory chip 22. Thus down-size of an entire device is accomplished. A boost converter having an inductor is used as a voltage boost circuit 40. Thus down-size of the entire device is accomplished.
    Type: Grant
    Filed: April 17, 2009
    Date of Patent: June 3, 2014
    Assignee: The University of Tokyo
    Inventors: Ken Takeuchi, Tadashi Yasufuku, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai
  • Publication number: 20140104952
    Abstract: A booster circuit is configured, such that: in response to a reading request for reading data from a flash memory, when a voltage of an output terminal detected by a voltage detection circuit is not higher than a voltage, an oscillator outputs a control clock signal of predetermined on time and off time to a transistor of a boost converter to perform switching control of the transistor; and when the voltage detection circuit detects that the voltage of the output terminal reaches a voltage, an oscillator outputs a control clock signal of an on time and an off time input from a selection circuit to a transistor of a boost converter to perform switching control of the transistor.
    Type: Application
    Filed: May 11, 2012
    Publication date: April 17, 2014
    Applicant: THE UNIVERSITY OF TOKYO
    Inventors: Ken Takeuchi, Teruyoshi Hatanaka, Koichi Ishida, Tadashi Yasufuku, Makoto Takamiya, Takayasu Sakurai
  • Publication number: 20140070858
    Abstract: A clock generation circuit 10 includes a resonant reactor connected with a half voltage supply point TV1, a resonant capacitor CL connected between a ground voltage supply point TVss and an output terminal TVout, a transistor MP1 connected between the resonant reactor Lr and the resonant capacitor CL, and a transistor MN1 connected with the output terminal TVout. In this configuration, signals in a wide range of frequencies can be output with low power consumption by adjusting the time when a clock signal ?1 applied to the gates of the transistors MP1 and MN1 is high.
    Type: Application
    Filed: September 9, 2013
    Publication date: March 13, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Hiroshi Fuketa, Makoto Takamiya, Takayasu Sakurai
  • Patent number: 8618870
    Abstract: The voltage Vdd is set to be lower than in the normal operation (step S100), then voltage is applied to each of the power-supply voltage applied node Vdd, the ground voltage applied node Vss, the semiconductor substrate and the well so that relative high voltage between the gate of turn-on transistor and the semiconductor substrate or the gate of turn-on transistor and well (steps S110 and S120). This process accomplishes rising of the threshold voltage of the transistor that is turned on, the reduction of the variation in the threshold voltage between a plurality of the transistors of the memory cell including latch circuit, and the improvement of the voltage characteristic of the memory cell.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: December 31, 2013
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Toshiro Hiramoto, Takayasu Sakurai, Makoto Suzuki
  • Patent number: 8514013
    Abstract: The channel number detecting circuit detects the operation channel number based on the output terminal voltage after falling down when the output terminal voltage falls down during the voltage boosting control, and the switching control circuit generates the control clock signal having the on-time and the off-time adjusted based on the operation channel number and performs the voltage boosting control using generating control clock signal. The voltage boosting control is properly performed based on the operation channel number when the operation channel number increase during performing the voltage boosting control. Thus boosting the power supply voltage up to a second voltage is accomplished.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: August 20, 2013
    Assignee: The University of Tokyo
    Inventors: Ken Takeuchi, Teruyoshi Hatanaka, Koichi Ishida, Tadashi Yasufuku, Makoto Takamiya, Takayasu Sakurai
  • Publication number: 20120212212
    Abstract: In a voltage detecting circuit, a transistor is configured as a P-type MOSFET, and includes a source connected with an input terminal, a gate connected with a ground voltage terminal and a drain connected with an output terminal. A transistor is configured as a P-type MOSFET, and includes a gate and a source connected with the output terminal and a drain connected with the ground terminal. Gate width and gate length of the transistor and gate width and gate length of the transistor are adjusted so that source-drain current flowing between the source and the drain of the transistor becomes equal to source-drain current flowing between the source and the drain of the transistor when the voltage applied to the input terminal is set to be preset trigger voltage. This configuration accomplishes detecting that the input voltage exceeds the trigger voltage with simple configuration.
    Type: Application
    Filed: February 14, 2012
    Publication date: August 23, 2012
    Inventors: Po-Hung CHEN, Makoto TAKAMIYA, Takayasu SAKURAI
  • Publication number: 20120182064
    Abstract: The voltage Vdd is set to be lower than in the normal operation (step S100), then voltage is applied to each of the power-supply voltage applied node Vdd, the ground voltage applied node Vss, the semiconductor substrate and the well so that relative high voltage between the gate of turn-on transistor and the semiconductor substrate or the gate of turn-on transistor and well (steps S110 and S120). This process accomplishes rising of the threshold voltage of the transistor that is turned on, the reduction of the variation in the threshold voltage between a plurality of the transistors of the memory cell including latch circuit, and the improvement of the voltage characteristic of the memory cell.
    Type: Application
    Filed: June 11, 2010
    Publication date: July 19, 2012
    Applicant: SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER
    Inventors: Toshiro Hiramoto, Takayasu Sakurai, Makoto Suzuki
  • Publication number: 20110298534
    Abstract: The channel number detecting circuit 50 detects the operation channel number Nch based on the the output terminal voltage Vpgm after falling down when the output terminal voltage Vpgm falls down during the voltage boosting control, and the switching control circuit 70 generates the control clock signal CLK having the on-time and the off-time adjusted based on the operation channel number Nch and performs the voltage boosting control using generating control clock signal CLK. The voltage boosting control is properly performed based on the operation channel number Nch when the operation channel number Nch increase during performing the voltage boosting control. Thus boosting the power supply voltage Vdd up to the voltage V2 is accomplished.
    Type: Application
    Filed: April 25, 2011
    Publication date: December 8, 2011
    Applicant: THE UNIVERSITY OF TOKYO
    Inventors: Ken TAKEUCHI, Teruyoshi HATANAKA, Koichi ISHIDA, Tadashi YASUFUKU, Makoto TAKAMIYA, Takayasu SAKURAI
  • Publication number: 20110260781
    Abstract: The interposer is disposed on an upper surface of the stacked structure formed by stacking a plurality of a DRAM chip and a plurality of a flash memory chip. Thus down-size of an entire device is accomplished. A boost converter having an inductor is used as a voltage boost circuit. Thus down-size of the entire device is accomplished in comparison to a voltage boost circuit using a charge pump connected in parallel with a plurality of a capacitance.
    Type: Application
    Filed: April 17, 2009
    Publication date: October 27, 2011
    Applicant: THE UNIVERSITY OF TOKYO
    Inventors: Ken Takeuchi, Tadashi Yasufuku, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai
  • Patent number: 7768790
    Abstract: An electronic circuit capable of efficiently transmitting signals in a case where signals are transmitted over substrates with three or more substrates three-dimensionally mounted. In the present invention, LSI chips are stacked in three layers, and a bus is formed over three chips. The first through the third transmitter coils 13a, 13b, 13c and the first through the third receiver coils 15a, 15b, 15c are formed by wiring on the first through the third LSI chips 11a, 11b, 11c. These three pairs of transmitter and receiver coils are disposed so that the centers of the openings thereof are coincident with each other, whereby three pairs of transmitter and receiver coils 13 and 15 form inductive coupling to enable communications.
    Type: Grant
    Filed: February 14, 2005
    Date of Patent: August 3, 2010
    Assignee: KEIO University
    Inventors: Tadahiro Kuroda, Daisuke Mizoguchi, Yusmeeraz Binti Yusof, Noriyuki Miura, Takayasu Sakurai
  • Publication number: 20090129031
    Abstract: A flat pressure sensor of the invention is prepared by processing a thin film of a polymer material to have plurality of substantially square openings 24. A planar member 22 of the flat pressure sensor thus obtained has a net-like structure including multiple element formation areas 26 and multiple bridging areas 28 that respectively bridge the multiple element formation areas 26. Pressure sensor elements 30 are provided in the multiple element formation areas 26 of the planar member 22. A wiring to the pressure sensor elements 30 is formed on the multiple bridging areas 28. The net-like structure enables the flat pressure sensor to be stretched in diagonal directions without arrangement of the bridging areas 28 and to be deformed to a curved surface. The flat pressure sensor of the invention is thus attached to a curved surface, for example, a spherical surface.
    Type: Application
    Filed: September 27, 2005
    Publication date: May 21, 2009
    Applicant: THE UNIVERSITY OF TOKYO
    Inventors: Takao Someya, Takayasu Sakurai, Hiroshi Kawaguchi, Tsuyoshi Sekitani