Patents by Inventor Takayasu Sakurai
Takayasu Sakurai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110298534Abstract: The channel number detecting circuit 50 detects the operation channel number Nch based on the the output terminal voltage Vpgm after falling down when the output terminal voltage Vpgm falls down during the voltage boosting control, and the switching control circuit 70 generates the control clock signal CLK having the on-time and the off-time adjusted based on the operation channel number Nch and performs the voltage boosting control using generating control clock signal CLK. The voltage boosting control is properly performed based on the operation channel number Nch when the operation channel number Nch increase during performing the voltage boosting control. Thus boosting the power supply voltage Vdd up to the voltage V2 is accomplished.Type: ApplicationFiled: April 25, 2011Publication date: December 8, 2011Applicant: THE UNIVERSITY OF TOKYOInventors: Ken TAKEUCHI, Teruyoshi HATANAKA, Koichi ISHIDA, Tadashi YASUFUKU, Makoto TAKAMIYA, Takayasu SAKURAI
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Publication number: 20110260781Abstract: The interposer is disposed on an upper surface of the stacked structure formed by stacking a plurality of a DRAM chip and a plurality of a flash memory chip. Thus down-size of an entire device is accomplished. A boost converter having an inductor is used as a voltage boost circuit. Thus down-size of the entire device is accomplished in comparison to a voltage boost circuit using a charge pump connected in parallel with a plurality of a capacitance.Type: ApplicationFiled: April 17, 2009Publication date: October 27, 2011Applicant: THE UNIVERSITY OF TOKYOInventors: Ken Takeuchi, Tadashi Yasufuku, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai
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Patent number: 7768790Abstract: An electronic circuit capable of efficiently transmitting signals in a case where signals are transmitted over substrates with three or more substrates three-dimensionally mounted. In the present invention, LSI chips are stacked in three layers, and a bus is formed over three chips. The first through the third transmitter coils 13a, 13b, 13c and the first through the third receiver coils 15a, 15b, 15c are formed by wiring on the first through the third LSI chips 11a, 11b, 11c. These three pairs of transmitter and receiver coils are disposed so that the centers of the openings thereof are coincident with each other, whereby three pairs of transmitter and receiver coils 13 and 15 form inductive coupling to enable communications.Type: GrantFiled: February 14, 2005Date of Patent: August 3, 2010Assignee: KEIO UniversityInventors: Tadahiro Kuroda, Daisuke Mizoguchi, Yusmeeraz Binti Yusof, Noriyuki Miura, Takayasu Sakurai
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Publication number: 20090129031Abstract: A flat pressure sensor of the invention is prepared by processing a thin film of a polymer material to have plurality of substantially square openings 24. A planar member 22 of the flat pressure sensor thus obtained has a net-like structure including multiple element formation areas 26 and multiple bridging areas 28 that respectively bridge the multiple element formation areas 26. Pressure sensor elements 30 are provided in the multiple element formation areas 26 of the planar member 22. A wiring to the pressure sensor elements 30 is formed on the multiple bridging areas 28. The net-like structure enables the flat pressure sensor to be stretched in diagonal directions without arrangement of the bridging areas 28 and to be deformed to a curved surface. The flat pressure sensor of the invention is thus attached to a curved surface, for example, a spherical surface.Type: ApplicationFiled: September 27, 2005Publication date: May 21, 2009Applicant: THE UNIVERSITY OF TOKYOInventors: Takao Someya, Takayasu Sakurai, Hiroshi Kawaguchi, Tsuyoshi Sekitani
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Publication number: 20070289772Abstract: The present invention has an object to provide an electronic circuit capable of efficiently transmitting signals in a case where signals are transmitted over substrates with three or more substrates three-dimensionally mounted. In the present invention, LSI chips are stacked in three layers, and a bus is formed over three chips. The first through the third transmitter coils 13a, 13b, 13c and the first through the third receiver coils 15a, 15b, 15c are formed by wiring on the first through the third LSI chips 11a, 11b, 11c. These three pairs of transmitter and receiver coils are disposed so that the centers of the openings thereof are coincident with each other, whereby three pairs of transmitter and receiver coils 13 and 15 form inductive coupling to enable communications.Type: ApplicationFiled: February 14, 2005Publication date: December 20, 2007Inventors: Tadahiro Kuroda, Daisuke Mizoguchi, Yusmeeraz Yusof, Noriyuki Miura, Takayasu Sakurai
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Patent number: 7266035Abstract: A memory cell array includes a plurality of memory cells arranged in a matrix form. A word line and a power supply line respectively are connected in common to the plurality of memory cells arranged in each row. A power supply line/word line control circuit is connected to each word line and each power supply line. In accessing the plurality of memory cells row by row, the control circuit raises the voltage of the power supply line and, after the voltage of the power supply line reaches the high voltage at all the positions, starts activation of the word line. On the other hand, in turning from the access state to the non-access state, the control circuit deactivates the word line and, after the voltage of the word line changes to the ground voltage at all the positions, changes the voltage of the power supply line to the low voltage.Type: GrantFiled: August 16, 2005Date of Patent: September 4, 2007Assignee: Semiconductor Technology Academic Research CenterInventors: Takayasu Sakurai, Hiroshi Kawaguchi, Robert Saliba Fayez
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Patent number: 7088084Abstract: A voltage control circuit is connected to a voltage source. The voltage control circuit changes voltages of n different values and outputs them to an output node of the voltage control circuit according to control signals. A first switch element is connected between the output node of the voltage control circuit and a reference voltage node, and a second switch element is connected between the output node of the voltage control circuit and an output node of the voltage source. The first switch element is controlled so as to be conductive when the voltage control circuit changes the voltage of the output node from a first voltage to a second voltage that is lower than the first voltage, and the second switch element is controlled so as to be conductive when the voltage control circuit changes the voltage of the output node from a second voltage to a first voltage.Type: GrantFiled: August 16, 2005Date of Patent: August 8, 2006Assignee: Semiconductor Technology Academic Research CenterInventors: Takayasu Sakurai, Hiroshi Kawaguchi, Kohei Onizuka
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Publication number: 20060039182Abstract: A memory cell array includes a plurality of memory cells arranged in a matrix form. A word line and a power supply line respectively are connected in common to the plurality of memory cells arranged in each row. A power supply line/word line control circuit is connected to each word line and each power supply line. In accessing the plurality of memory cells row by row, the control circuit raises the voltage of the power supply line and, after the voltage of the power supply line reaches the high voltage at all the positions, starts activation of the word line. On the other hand, in turning from the access state to the non-access state, the control circuit deactivates the word line and, after the voltage of the word line changes to the ground voltage at all the positions, changes the voltage of the power supply line to the low voltage.Type: ApplicationFiled: August 16, 2005Publication date: February 23, 2006Applicant: Semiconductor Technology Academic Research CenterInventors: Takayasu Sakurai, Hiroshi Kawaguchi, Robert Fayez
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Publication number: 20060038544Abstract: A voltage control circuit is connected to a voltage source. The voltage control circuit changes voltages of n different values and outputs them to an output node of the voltage control circuit according to control signals. A first switch element is connected between the output node of the voltage control circuit and a reference voltage node, and a second switch element is connected between the output node of the voltage control circuit and an output node of the voltage source. The first switch element is controlled so as to be conductive when the voltage control circuit changes the voltage of the output node from a first voltage to a second voltage that is lower than the first voltage, and the second switch element is controlled so as to be conductive when the voltage control circuit changes the voltage of the output node from a second voltage to a first voltage.Type: ApplicationFiled: August 16, 2005Publication date: February 23, 2006Applicant: Semiconductor Technology Academic Research CenterInventors: Takayasu Sakurai, Hiroshi Kawaguchi, Kohei Onizuka
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Patent number: 6529042Abstract: A semiconductor integrated circuit of the present invention has a CMOS circuit 1 composed of a first MOSFET and a switch 2 composed of a second MOSFET which are connected in series. Then, a circuit-driving voltage and a switch-driving voltage are applied independently to the CMOS circuit 1 and the switch 2. The switch-driving voltage is larger than the circuit-driving voltage.Type: GrantFiled: April 13, 2000Date of Patent: March 4, 2003Assignee: University of TokyoInventors: Toshiro Hiramoto, Takayasu Sakurai, Takashi Inukai
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Patent number: 6215159Abstract: CMOS logic circuit CM is of a structure in which the threshold value of constituent transistors MP1, MN1, etc. thereof is set to value lower than ordinary value, and the threshold value of a stand-by state current control P-channel MOS transistor MP2 is set to value higher than the threshold value of the transistors MP1, MN1, etc. constituting the CMOS logic circuit CM. A level conversion circuit 10 outputs a signal in which low level indicates negative voltage and high level indicates the same potential VDD as that of the first power supply line P1 in dependency upon high level and low level of signal applied to control input terminal SIG to thereby carry out ON/OFF control of the P-channel MOS transistor MP2.Type: GrantFiled: March 24, 1998Date of Patent: April 10, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Tetsuya Fujita, Gensoh Matsubara, Tadahiro Kuroda, Takayasu Sakurai
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Patent number: 6037805Abstract: To minimize the power consumption, the disclosed semiconductor integrated circuit device, comprises; a bias circuit for generating a predetermined voltage fixed between a first supply voltage and a second supply voltage; a driver circuit for receiving an inversion input signal and a non-inversion input signal each vibrating between the first and second supply voltages, for converting the received input signals into a signal vibrating between an output voltage of the bias circuit and the first supply voltage, and for driving a transfer path by the converted signal; a voltage divider circuit for dividing an output voltage of the bias circuit; and a receiver circuit for detecting the signal for driving the transfer path by use of an output of the voltage divider circuit as a reference voltage, and for converting the detected signal into a signal vibrating between the first supply voltage and the second supply voltage.Type: GrantFiled: March 29, 1999Date of Patent: March 14, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Tadahiro Kuroda, Takayasu Sakurai
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Patent number: 5933029Abstract: To minimize the power consumption, the disclosed semiconductor integrated circuit device, comprises; a bias circuit for generating a predetermined voltage fixed between a first supply voltage and a second supply voltage; a driver circuit for receiving an inversion input signal and a non-inversion input signal each vibrating between the first and second supply voltages, for converting the received input signals into a signal vibrating between an output voltage of the bias circuit and the first supply voltage, and for driving a transfer path by the converted signal; a voltage divider circuit for dividing an output voltage of the bias circuit; and a receiver circuit for detecting the signal for driving the transfer path by use of an output of the voltage divider circuit as a reference voltage, and for converting the detected signal into a signal vibrating between the first/supply voltage and the second supply voltage.Type: GrantFiled: April 28, 1997Date of Patent: August 3, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Tadahiro Kuroda, Takayasu Sakurai
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Patent number: 5673214Abstract: Disclosed is an improved discrete cosine transform processor comprising an input unit for receiving image data to be processed, a storage unit for previously storing a result of a multiplication and accumulation calculation effected beforehand with respect to image input data and transform matrix components so that the same value is read from the same read line; a decoding unit for selecting the read line, in which each bit value of the image input data composed of a plurality of bits serves as a piece of address data; an accumulation unit for accumulating the data read from the storage unit and an output unit for outputting a result of the accumulation processing as output data. The storage unit uses the common data in common when effecting the multiplication and accumulation calculation, and, hence, a storage capacity is reduced, thereby making it possible to decrease a chip area.Type: GrantFiled: August 28, 1996Date of Patent: September 30, 1997Assignee: Kabushiki Kaisha ToshibaInventors: Lee-Sup Kim, Tetsu Nagamatsu, Takayasu Sakurai
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Patent number: 5596520Abstract: A full adder circuit has a plurality of full adders each provided for each bit. Each full adder has: a calculation block (31a) responsive to a first carry signal (C) given by a preceding stage bit as a differential signal and two external input data (A1, B1) to be added at a present stage bit, for outputting addition data calculated on the basis of the first carry signal and the external input data as two differential signals, and further outputting a second carry signal (/C) to a succeeding bit as a differential signal indicative of whether a carry is generated by the present stage bit or not. Each full adder also has a latch type sense amplifier (16a) for outputting an addition result (SUM) of the present stage bit, after having differentially amplified and latched the addition data outputted by the calculation block.Type: GrantFiled: October 4, 1994Date of Patent: January 21, 1997Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyuki Hara, Takayasu Sakurai
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Patent number: 5539331Abstract: A field programmable gate array comprises: a first wire group (8) composed of a plurality of first wires; a second wire group (7) composed of a plurality of second wires; switching sections (9) provided at least one intersection between the first and second wires of the first and second wire groups (8, 7), for determining connection and disconnection between both when programmed; and a basis cell (6B) having a first transmission gate (4) turned on in response to a high gate voltage and a second transmission gate (5) turned on in response to a low gate voltage, gates of the first and second transmission gates (4, 5) being connected to each other as a common gate or being connectable to each other as a common gate by the switching sections when programmed, input and output terminals and the common gates of the first and second transmission gates (4, 5) being connected to any of the first wires of the first wire group (8), respectively.Type: GrantFiled: May 4, 1994Date of Patent: July 23, 1996Assignee: Kabushiki Kaisha ToshibaInventors: Fumitoshi Hatori, Kazutaka Nogami, Takayasu Sakurai, Makoto Ichida
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Patent number: 5459342Abstract: A field programmable gate array, comprises: a plurality of circuit blocks each having logic circuits; at least one spare circuit block having logic circuits; a set of interconnections including at least one interconnection for connecting at least one of the circuit blocks and the at least one spare circuit programmably; and at least one connecting element disposed on the interconnection of the set of interconnections which turns its status from a turned-on state to a turned-off state or vice versa when programmed. When any one of the circuit blocks is defective, since the defective circuit block can be replaced with the spare circuit block, it is possible to retain any desired functions of the logic circuits by programming the connecting means, thus improving the production yield of the field programmable gate array and thereby reducing the manufacturing cost thereof.Type: GrantFiled: November 2, 1993Date of Patent: October 17, 1995Assignee: Kabushiki Kaisha ToshibaInventors: Kazutaka Nogami, Takayasu Sakurai, Fumitoshi Hatori
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Patent number: 5434517Abstract: An ECL output buffer circuit is constituted by an output buffer circuit main portion and its control circuit. In the output buffer circuit main portion, an output from a differential switch is input to the base of a bipolar transistor (emitter follower). The emitter of the bipolar transistor is connected to an output terminal. A ground potential is applied to the collector of the bipolar transistor. One end of the channel conductive path of a MOS transistor is connected to the base of the bipolar transistor. The other end of the channel conductive path is connected to a power-supply terminal via a constant-current source. The control circuit controls the ON/OFF operation of the MOS transistor and the output level of the bipolar transistor. When the output buffer circuit main portion is to be set in a standby state, the control circuit performs control to set the MOS transistor in an ON state and set the output of the bipolar transistor at low level.Type: GrantFiled: March 21, 1994Date of Patent: July 18, 1995Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyuki Hara, Takayasu Sakurai
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Patent number: 5294911Abstract: According to this invention, a bit data comparing section has a plurality of groups each having a plurality of bit comparators. Each of the plurality of bit comparators compares one bit of address data input to the bit comparator with bit data stored in the bit comparator in advance and outputs a comparison result. Output data from a plurality of bit comparators belonging to one group are unified by one subsense line belonging to the group and input to a control terminal of a switching element. The switching element performs a switching operation in accordance with the input data. A main sense line is connected to the switching element, and a load circuit is connected between the main sense line and a power supply terminal.Type: GrantFiled: February 27, 1992Date of Patent: March 15, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Masanori Uchida, Takayasu Sakurai
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Patent number: 5258957Abstract: In a semiconductor memory device of a divided bit line system, read signals from memory cell blocks are sense-amplified together by a single differential bit line sense amplifier. The bit line sense amplifier includes a plurality of first transistors, the base electrodes of which are connected to local bit lines of the memory cell blocks, the emitter electrodes of which are commonly connected to corresponding main bit lines, and the collector electrodes of which are connected to a first power supply node, a second transistor, which forms a differential pair with each of the first transistors, the base electrode of which is applied with a reference bias potential, and the emitter electrode of which is connected to the main bit lines, a current source connected between the emitter electrode of the second transistor, and a second power supply node, and a load circuit connected between the collector electrode of the second transistor and the first power supply node.Type: GrantFiled: March 11, 1992Date of Patent: November 2, 1993Assignee: Kabushiki Kaisha ToshibaInventors: Katsuhiro Seta, Hiroyuki Hara, Takayasu Sakurai, Yoshinori Watanabe