Abstract: A semiconductor memory device has a plurality of memory cells arranged in a two-dimensional matrix array, word lines for connecting memory cells of each row to a row decoder, and bit lines for connecting memory cells of each column to a column decoder. The word lines include first word lines each of which is connected to several memory cells in each column section of one row. The word lines also include a second word line connected to the first word lines of each row through corresponding switches. In response to a column address signal, one of the switches of each row is turned on, so that one of the first word lines is connected to the corresponding second word line.

Abstract: In a memory device, a plurality of memory cells are connected to bit line pairs. A precharge circuit is controlled by a chip enable signal during a stand-by state and by an address transition detector signal during an active state, to charge the bit line pairs up to a given power source voltage.

Abstract: In the semiconductor memory device according to the present invention, when there is a defective portion in the memory cells, those memory cells are replaced by redundant memory cells. When defective portions are discovered in the memory cells, the fuse elements corresponding to the memory cells having the defective portions are cut off. Voltages of the select lines connected to the memory cells having the defective portions are held at an L level by the resistors. Due to this, the memory cells having the defective portions are not selected.

Abstract: Disclosed is a semiconductor memory device in which a group of memory cells consists of a plurality of memory sections, each memory section is provided with a first data line, and a second data line is provided for connecting together the first data lines.