Patents by Inventor Takayoshi Shimura

Takayoshi Shimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150318372
    Abstract: A semiconductor device according to the present invention has a MIS structure that includes a semiconductor layer, a gate insulating film in contact with the semiconductor layer, and a gate electrode formed on the gate insulating film, and the gate insulating film includes an AlON layer with a nitrogen composition of 5% to 40%. A semiconductor device is thereby provided with which electron trapping in the gate insulating film can be reduced and shifting of a threshold voltage Vth can be suppressed.
    Type: Application
    Filed: December 2, 2013
    Publication date: November 5, 2015
    Inventors: Heiji WATANABE, Takuji HOSOI, Takayoshi SHIMURA, Ryota NAKAMURA, Yuki NAKANO, Shuhei MITANI, Takashi NAKAMURA, Hirokazu ASAHARA
  • Publication number: 20150144967
    Abstract: A semiconductor device includes a semiconductor layer made of first conductivity type SiC; a second conductivity type well region formed on the semiconductor layer and having a channel region; a first conductivity type source region formed on the well region and including a first region adjacent to the well region and a second region adjacent to the first region; a gate insulating film formed on the semiconductor layer and having a first portion that contacts the first region; a second portion that contacts the well region and that has a thickness that is the same as that of the first portion; and a third portion that contacts the second region and that has a thickness that is greater than that of the first portion; and a gate electrode formed on the gate insulating film and opposed to the channel region where a channel is formed through the gate insulating film.
    Type: Application
    Filed: January 21, 2015
    Publication date: May 28, 2015
    Inventors: Shuhei MITANI, Yuki NAKANO, Heiji WATANABE, Takayoshi SHIMURA, Takuji HOSOI, Takashi KIRINO
  • Patent number: 8969877
    Abstract: A semiconductor device includes a semiconductor layer made of first conductivity type SiC; a second conductivity type well region formed on the semiconductor layer and having a channel region; a first conductivity type source region formed on the well region and including a first region adjacent to the well region and a second region adjacent to the first region; a gate insulating film formed on the semiconductor layer and having a first portion that contacts the first region; a second portion that contacts the well region and that has a thickness that is the same as that of the first portion; and a third portion that contacts the second region and that has a thickness that is greater than that of the first portion; and a gate electrode formed on the gate insulating film and opposed to the channel region where a channel is formed through the gate insulating film.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: March 3, 2015
    Assignee: Rohm Co., Ltd.
    Inventors: Shuhei Mitani, Yuki Nakano, Heiji Watanabe, Takayoshi Shimura, Takuji Hosoi, Takashi Kirino
  • Publication number: 20140138708
    Abstract: A method of manufacturing a semiconductor device includes the steps of forming a silicon oxide film on a silicon carbide substrate, annealing the silicon carbide substrate and the silicon oxide film in gas containing hydrogen, and forming an aluminum oxynitride film on the silicon oxide film after the annealing of the silicon carbide substrate and the silicon oxide film.
    Type: Application
    Filed: January 7, 2014
    Publication date: May 22, 2014
    Applicant: ROHM CO., LTD.
    Inventors: Shuhei MITANI, Yuki NAKANO, Heiji WATANABE, Takayoshi SHIMURA, Takuji HOSOI, Takashi KIRINO
  • Publication number: 20140094027
    Abstract: Provided is a method of forming a gate insulating film for use in a MOSFET for a power device. An AlN film is formed on a SiC substrate of a wafer W and then the formation of an AlO film and the formation of an AlN film on the formed AlO film are repeated, thereby forming an AlON film having a laminated structure in which AlO films and AlN films are alternately laminated. A heat treatment is performed on the AlON film having the laminated structure.
    Type: Application
    Filed: October 2, 2013
    Publication date: April 3, 2014
    Applicants: OSAKA UNIVERSITY, TOKYO ELECTRON LIMITED
    Inventors: Shuji AZUMO, Yusaku KASHIWAGI, Yuichiro MOROZUMI, Yu WAMURA, Katsushige HARADA, Kosuke TAKAHASHI, Heiji WATANABE, Takayoshi SHIMURA, Takuji HOSOI
  • Patent number: 8669624
    Abstract: Provided are a semiconductor device which enables reduction of diffusion of Si in the manufacturing process of an MIPS element and suppression of an increase in EOT, and a method of manufacturing the same. An embodiment of the present invention is a semiconductor device including a field effect transistor having a gate insulating film provided on a silicon substrate and a gate electrode provided on the gate insulating film. The gate electrode is a stack-type electrode including a conductive layer containing at least Ti, N, and O (oxygen) and a silicon layer provided on the conductive layer, and the concentration of oxygen in the conductive layer is highest in the side of the silicon layer.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: March 11, 2014
    Assignee: Canon Anelva Corporation
    Inventors: Naomu Kitano, Takashi Minami, Nobuo Yamaguchi, Takuya Seino, Takashi Nakagawa, Heiji Watanabe, Takayoshi Shimura, Takuji Hosoi
  • Patent number: 8653533
    Abstract: A method of manufacturing a semiconductor device includes the steps of forming a silicon oxide film on a silicon carbide substrate, annealing the silicon carbide substrate and the silicon oxide film in gas containing hydrogen, and forming an aluminum oxynitride film on the silicon oxide film after the annealing of the silicon carbide substrate and the silicon oxide film.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: February 18, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Shuhei Mitani, Yuki Nakano, Heiji Watanabe, Takayoshi Shimura, Takuji Hosoi, Takashi Kirino
  • Publication number: 20130285158
    Abstract: Provided are a semiconductor device which enables reduction of diffusion of Si in the manufacturing process of an MIPS element and suppression of an increase in EOT, and a method of manufacturing the same. An embodiment of the present invention is a semiconductor device including a field effect transistor having a gate insulating film provided on a silicon substrate and a gate electrode provided on the gate insulating film. The gate electrode is a stack-type electrode including a conductive layer containing at least Ti, N, and O (oxygen) and a silicon layer provided on the conductive layer, and the concentration of oxygen in the conductive layer is highest in the side of the silicon layer.
    Type: Application
    Filed: July 26, 2012
    Publication date: October 31, 2013
    Applicant: CANON ANELVA CORPORATION
    Inventors: Naomu Kitano, Takashi Minami, Nobuo Yamaguchi, Takuya Seino, Takashi Nakagawa, Heiji Watanabe, Takayoshi Shimura, Takuji Hosoi
  • Publication number: 20120223338
    Abstract: A method of manufacturing a semiconductor device includes the steps of forming a silicon oxide film on a silicon carbide substrate, annealing the silicon carbide substrate and the silicon oxide film in gas containing hydrogen, and forming an aluminum oxynitride film on the silicon oxide film after the annealing of the silicon carbide substrate and the silicon oxide film.
    Type: Application
    Filed: September 2, 2010
    Publication date: September 6, 2012
    Applicant: Rohm Co. Ltd.
    Inventors: Shuhei Mitani, Yuki Nakano, Heiji Watanabe, Takayoshi Shimura, Takuji Hosoi, Takashi Kirino