Patents by Inventor Takayuki Hashimoto

Takayuki Hashimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9252137
    Abstract: A semiconductor substrate capable of detecting operating current of a MOSFET and diode current in a miniaturized MOSFET such as a trench-gate type MOSFET is provided. A semiconductor substrate includes a main current region and a current sensing region in which current smaller than main current flowing in the main current region flows. The main current region has a source electrode disposed on a main surface, the source electrode being in contact with a p-type semiconductor region (body) and an n+-type semiconductor region (source), and the current sensing region has a MOSFET current detecting electrode and a diode current detecting electrode on a main surface, the MOSFET current detecting electrode being in contact with the p-type semiconductor region (body) and the n+-type semiconductor region (source), the diode current detecting electrode being in contact with the p-type semiconductor region (body).
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: February 2, 2016
    Assignee: Renesas Electronics Corporation
    Inventor: Takayuki Hashimoto
  • Publication number: 20160013300
    Abstract: A semiconductor device according to the present invention includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type adjacent to the first semiconductor layer and having an impurity concentration lower than the first semiconductor layer; a third semiconductor layer of a second conductivity type adjacent to the second semiconductor layer; a fourth semiconductor layer of the first conductivity type located within the third semiconductor layer; a first electrode coupled to the third semiconductor layer and the fourth semiconductor layer; a second electrode coupled to the first semiconductor layer; and an insulated gate provided over the respective surfaces of the third semiconductor layer and the fourth semiconductor layer, wherein peak value of the impurity concentration of the third semiconductor layer is in the range of 2×1016 cm?3 or more and 5×1018 cm?3 or less.
    Type: Application
    Filed: February 25, 2013
    Publication date: January 14, 2016
    Inventors: Takayuki HASHIMOTO, Mutsuhiro MORI
  • Publication number: 20160013299
    Abstract: A semiconductor device according to the present invention includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type, which is adjacent to the first semiconductor layer and has an impurity concentration lower than the first semiconductor layer; a third semiconductor layer adjacent to the second semiconductor layer; a first electrode electrically coupled to the third semiconductor layer; a second electrode electrically coupled to the first semiconductor layer; and an insulated gate provided over the surface of the third semiconductor layer. Then, an end portion of the insulated gate is located at a position distant from the junction part between the second semiconductor layer and the third semiconductor layer within the surface of the third semiconductor layer.
    Type: Application
    Filed: February 25, 2013
    Publication date: January 14, 2016
    Applicant: Hitachi, Ltd.
    Inventors: Takayuki HASHIMOTO, Mutsuhiro MORI
  • Publication number: 20150324026
    Abstract: A processing apparatus generates a command in accordance with a size of the coordinate input area and a distance between two touch inputs on the coordinate input area. When a distance between two touch inputs on a first coordinate input area larger than a second coordinate input area changes to a first distance, a command corresponding to a second distance longer than the first distance is generated. When a distance between two touch inputs on the second coordinate input area smaller than the first coordinate input area changes to a third distance, a command corresponding to the third distance is generated.
    Type: Application
    Filed: April 24, 2015
    Publication date: November 12, 2015
    Inventors: Takayuki Hashimoto, Katsuyuki Kobayashi
  • Publication number: 20150303288
    Abstract: The present invention provides a switching device (100) for power conversion in which a first gate electrode (6), a p-type channel layer (2) having an n-type emitter region (3), a second gate electrode (13), and a p-type floating layer (15) are repeatedly arranged in order on the surface side of an n-type semiconductor substrate (1). An interval a between the two gates (6, 13) that sandwich the p-type channel layer (2) is configured to be smaller than an interval b between the two gates (13, 6) that sandwich the p-type floating layer (15). The first gate electrode (6) and the second gate electrode (13) are both supplied with drive signals having a time difference in drive timing.
    Type: Application
    Filed: September 7, 2012
    Publication date: October 22, 2015
    Applicant: Hitachi, Ltd.
    Inventors: Takayuki HASHIMOTO, Mutsuhiro MORI, Masahiro MASUNAGA
  • Publication number: 20150279979
    Abstract: There is provided a semiconductor device including a first emitter layer of a first conductivity type, a drift layer of a second conductivity type, adjacent to the first emitter layer, a channel layer of the first conductivity type, adjacent to the drift layer, a second emitter layer of the second conductivity type, adjacent to the channel layer, a collector electrode electrically coupled to the first emitter layer, an emitter electrode electrically coupled to the second emitter layer, a first trench-gate electrode for controlling on and off of an electric current flowing between the collector electrode and the emitter electrode, and a second trench-gate electrode for controlling a turn-off power loss. The semiconductor device further includes a thyristor unit made up of the first emitter layer, the drift layer, the channel layer, and the second emitter layer.
    Type: Application
    Filed: October 5, 2012
    Publication date: October 1, 2015
    Inventors: Takayuki Hashimoto, Mutsuhiro Mori, Masahiro Masunaga
  • Patent number: 9082213
    Abstract: When an image in a virtual space in which a virtual object is arranged is generated using a ray tracing method, and when it is determined that a ray which is generated in accordance with the ray tracing method successively intersected an approximate virtual object such as a hand which is a real object at lest twice, an image corresponding to a first intersection is generated in accordance with the ray emitted to the first intersection.
    Type: Grant
    Filed: November 5, 2008
    Date of Patent: July 14, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masakazu Fujiki, Kaname Tomite, Yasuo Katano, Takayuki Hashimoto
  • Publication number: 20150162429
    Abstract: A semiconductor device (10) includes an n-type drift layer (11) that is a semiconductor substrate; a p-type region (12) and an n-type region (13) that are formed on a surface of the semiconductor substrate and serving as anode regions; a high-concentration n-type region (15) formed on a back surface of the semiconductor substrate and serving as a cathode region; and an anode electrode (1). The semiconductor substrate includes, on its surface, a structure in which the p-type region (12) and the n-type region (13) are adjacent to each other, wherein the p-type region (12) is connected to the anode electrode (1), and the n-type region (13) is connected to the anode electrode (1) via a switch (14). A control unit (40) is connected to a control terminal of the switch (14). In a conduction state of the semiconductor device (10), the control unit (40) outputs a high-frequency pulse to the control terminal of the switch (14) to turn on and off the switch (14).
    Type: Application
    Filed: January 26, 2012
    Publication date: June 11, 2015
    Applicant: Hitachi, Ltd.
    Inventors: Takayuki Hashimoto, Masahiro Masunaga
  • Patent number: 8982102
    Abstract: A coordinate input apparatus includes a light projecting unit configured to project light parallelly to an effective coordinate input region, a reflection unit configured to retroreflect the light projected by the light projecting unit, and a light receiving unit configured to receive light from the light projecting unit or the reflection unit. The coordinate input apparatus includes a moving unit configured to move a set of the light projecting unit, light receiving unit, and reflection unit in a direction perpendicular to the effective coordinate input region in order to ensure a light amount with which a pointed position in the effective coordinate input region can be calculated based on variations of a light amount distribution obtained from the light receiving unit.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: March 17, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hirokuni Takano, Yuichiro Yoshimura, Katsuyuki Kobayashi, Ritsuo Machii, Takuto Kawahara, Takayuki Hashimoto, Naoki Umemura, Hajime Sato, Takayuki Komine, Akihiro Matsushita
  • Patent number: 8941622
    Abstract: A coordinate input apparatus includes a first housing and a second housing each of which incorporate at least two sensor units each including one of the light projecting unit and one of the light receiving unit. A pointed position to an effective coordinate input region is calculated based on variations of a light amount distribution obtained from the light receiving units of each of the first and second housings. In each of the first and second housings, the field range of a light receiving unit is almost parallel to the effective coordinate input region, the optical axis direction of the light receiving unit is a direction perpendicular to a line segment connecting the barycenters of at least two sensor units in a single housing, and the field range is set to be asymmetric to the optical axis direction.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: January 27, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Katsuyuki Kobayashi, Hirokuni Takano, Yuichiro Yoshimura, Hajime Sato, Ritsuo Machii, Takuto Kawahara, Takayuki Hashimoto, Takayuki Komine, Akihiro Matsushita, Naoki Umemura
  • Publication number: 20140367685
    Abstract: A semiconductor substrate capable of detecting operating current of a MOSFET and diode current in a miniaturized MOSFET such as a trench-gate type MOSFET is provided. A semiconductor substrate includes a main current region and a current sensing region in which current smaller than main current flowing in the main current region flows. The main current region has a source electrode disposed on a main surface, the source electrode being in contact with a p-type semiconductor region (body) and an n+-type semiconductor region (source), and the current sensing region has a MOSFET current detecting electrode and a diode current detecting electrode on a main surface, the MOSFET current detecting electrode being in contact with the p-type semiconductor region (body) and the n+-type semiconductor region (source), the diode current detecting electrode being in contact with the p-type semiconductor region (body).
    Type: Application
    Filed: September 2, 2014
    Publication date: December 18, 2014
    Inventor: Takayuki HASHIMOTO
  • Patent number: 8901838
    Abstract: The semiconductor device is included in the LED driving circuit (current regulator) of driving the LED array (with series-connected number m×parallel-connected number n), and is formed of a plurality (n pieces) of LED driving devices of controlling a current (constant-current driving) flowing in each string. A vertical semiconductor device, for example, a vertical MOSFET is used as the LED driving device. Both of a main device functioning as a constant-current driving device and a subsidiary device functioning as a circuit-breaking switch during dimming are formed inside a chip of the device, which are formed of the vertical semiconductor devices. In a first surface of the device, each source region of the main device and the subsidiary device is formed so as to be insulated from each other through an isolation region.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: December 2, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Noboru Akiyama, Takayuki Hashimoto, Takashi Hirao, Nobuyoshi Matsuura, Hideo Ishii
  • Publication number: 20140334212
    Abstract: A semiconductor device of this invention (an IGBT with a built-in diode) includes: an n?-type drift layer 1; a p-type channel region 2 that is arranged in contact with the surface side of this n?-type drift layer 1; a gate electrode 5 that is provided in a trench T provided so as to penetrate this p-type channel region 2 and reach to the n?-type drift layer 1 through a gate insulating film 3; an n-type source region 4 that is provided so as to contact the trench T on the surface side of the p-type channel region 2; a high-concentration n-type region 6 that is arranged in contact with the back side of the n?-type drift layer 1; and a high-concentration p-type region 7 that is arranged in contact with the back side of this high-concentration n-type region 6; in which a junction of the high-concentration n-type region 6 and the high-concentration p-type region 7 is a tunnel junction. According to this semiconductor device, it is possible to form the IGBT and the diode on a single chip.
    Type: Application
    Filed: December 15, 2011
    Publication date: November 13, 2014
    Applicant: Hitachi, Ltd.
    Inventors: Takayuki Hashimoto, Mutsuhiro Mori
  • Patent number: 8841720
    Abstract: A semiconductor substrate capable of detecting operating current of a MOSFET and diode current in a miniaturized MOSFET such as a trench-gate type MOSFET is provided. A semiconductor substrate includes a main current region and a current sensing region in which current smaller than main current flowing in the main current region flows. The main current region has a source electrode disposed on a main surface, the source electrode being in contact with a p-type semiconductor region (body) and an n+-type semiconductor region (source), and the current sensing region has a MOSFET current detecting electrode and a diode current detecting electrode on a main surface, the MOSFET current detecting electrode being in contact with the p-type semiconductor region (body) and the n+-type semiconductor region (source), the diode current detecting electrode being in contact with the p-type semiconductor region (body).
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 23, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Takayuki Hashimoto
  • Patent number: 8698804
    Abstract: Upon generation of an image of a virtual space on which a virtual object is laid out using a ray tracing method, an approximate virtual object, which is configured by at least one virtual element to approximate the shape of a physical object, is laid out on the virtual space. Then, intersect determination between a ray generated based on the ray tracing method and an object on the virtual space is executed. As a result of the intersect determination, when the ray and the approximate virtual object have a predetermined intersect state, a pixel corresponding to the ray is generated based on a ray before the predetermined intersect state is reached.
    Type: Grant
    Filed: November 5, 2008
    Date of Patent: April 15, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kaname Tomite, Masakazu Fujiki, Yasuo Katano, Takayuki Hashimoto
  • Patent number: 8692805
    Abstract: A coordinate input apparatus for making an input by bringing a pointing device into contact with an input area of an apparatus main body is provided, wherein the pointing device comprises: a timer configured to generate a transmission cycle by timekeeping; a detection unit configured to detect the presence/absence of an input instruction according to the presence/absence of contact of the pointing device with the input area; wherein when the detection unit detects the presence of the input instruction, and then detects the absence of the input instruction, the timer continues timekeeping of the transmission cycle during a predetermined holding period.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: April 8, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takayuki Hashimoto
  • Patent number: 8664716
    Abstract: In a lateral-type power MOSFET, high breakdown voltage is achieved with suppressing to increase a cell pitch, and a feedback capacity and an ON resistance are decreased. An n? type silicon region having a high resistance to be a region of maintaining a breakdown voltage is vertically provided with respect to a main surface of an n+ type silicon substrate, and the n? type silicon region having the high resistance is connected to the n+ type silicon substrate. Also, a conductive substance is filled through an insulating substance inside a trench formed to reach the n+ type silicon substrate from the main surface of the n+ type silicon substrate so as to contact with the n? type silicon region having the high resistance, and the conductive substance is electrically connected to a source electrode.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: March 4, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Takayuki Hashimoto, Takashi Hirao, Noboru Akiyama
  • Patent number: 8658328
    Abstract: A stack structure for a solid oxide fuel cell includes a plurality of stacked single cells, each having a fuel electrode layer including a fuel electrode and an air electrode layer including an air electrode, the fuel electrode layer and the air electrode layer being arranged opposite each other on either side of a solid electrolyte, separators arranged between the stacked single cells to separate the single cells, and non-porous seal parts located within the fuel electrode layer and the air electrode layer, are equivalent to either the separators or the solid electrolyte at least in terms of thermal expansion and contraction characteristics, and are integrated with an edge of the fuel electrode or an edge of the air electrode, and also with the adjacent separator and the adjacent solid electrolyte.
    Type: Grant
    Filed: March 26, 2009
    Date of Patent: February 25, 2014
    Assignees: Japan Fine Ceramics Center, FCO Power, Inc.
    Inventors: Seiichi Suda, Kaori Jono, Fumio Hashimoto, Takayuki Hashimoto
  • Patent number: 8643102
    Abstract: A control device of a semiconductor device is provided. The control device of a semiconductor device is capable of reducing both ON resistance and feedback capacitance in a hollow-gate type planar MOSFET to which a second gate electrode is provided or a trench MOSFET to which a second gate electrode is provided. In the control device controlling driving of a hollow-gate type planar MOSFET to which a second gate electrode is provided or a trench MOSFET to which a second gate electrode is provided, a signal of tuning ON or OFF is outputted to a gate electrode in a state of outputting a signal of turning OFF to the second gate electrode.
    Type: Grant
    Filed: September 10, 2011
    Date of Patent: February 4, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Takayuki Hashimoto, Masahiro Masunaga
  • Patent number: 8638577
    Abstract: In a non-isolated DC/DC converter, a reference potential for a low-side pre-driver which drives a gate of a low-side MOSFET is applied from a portion except for a main circuit passing through a high-side MOSFET and the low-side MOSFET so that a parasitic inductance between a source of the low-side MOSFET and the pre-driver is increased without increasing the sum of parasitic inductances in the main circuit and negative potential driving of the gate of the low-side MOSFET can be performed and a self turn-on phenomenon can be prevented without adding any member and changing drive system.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: January 28, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Masaki Shiraishi, Takayuki Hashimoto, Noboru Akiyama