Patents by Inventor Takayuki Iwasaki

Takayuki Iwasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040227547
    Abstract: A power MOS-FET is used as a high side switch transistor for a non-insulated DC/DC converter. An electrode section that serves as a source terminal of the power MOS-FET is connected to one outer lead and two outer leads via bonding wires respectively. The outer lead is an external terminal connected to a path for driving the gate. Each of the outer leads is an external terminal connected to a main current path. Owing to the connection of the main current path and the gate driving path in discrete form, the influence of parasitic inductance can be reduced and voltage conversion efficiency can be improved.
    Type: Application
    Filed: May 3, 2004
    Publication date: November 18, 2004
    Inventors: Masaki Shiraishi, Takayuki Iwasaki, Nobuyoshi Matsuura, Tomoaki Uno
  • Publication number: 20040227163
    Abstract: The gate resistance of a power MOSFET in a semiconductor chip is reduced and the reliability and yield of the gate of the power MOSFET are improved The semiconductor chip includes two or more control electrode pads functioning as control electrodes for a power semiconductor device formed within a semiconductor chip. The two or more control electrode pads are distributed within the periphery of the gate area of the power semiconductor device such that the gate resistance of the power semiconductor device can be reduced. The two or more control electrode pads are connected via bumps or a conductive bonding material to an electrode layer of a multilayer circuit board disposed outside the semiconductor chip.
    Type: Application
    Filed: February 20, 2004
    Publication date: November 18, 2004
    Inventors: Kozo Sakamoto, Takayuki Iwasaki, Masaki Shiraishi
  • Publication number: 20040079996
    Abstract: The number of design processes for fabricating semiconductor devices can be reduced by parallel connection of a plurality of unit bipolar transistors Qu that are completely electrically isolated from each other in a semiconductor layer of an SOI substrate 1 to form a bipolar transistor having a large current capacity.
    Type: Application
    Filed: October 21, 2003
    Publication date: April 29, 2004
    Applicant: Hitachi, Ltd. and Hitachi ULSI Systems Co., Ltd.
    Inventors: Yoichi Tamaki, Takayuki Iwasaki, Kousuke Tsuji, Chiyoshi Kamada
  • Patent number: 6662344
    Abstract: The number of design processes for fabricating semiconductor devices can be reduced by parallel connection of a plurality of unit bipolar transistors Qu that are completely electrically isolated from each other in a semiconductor layer of an SOI substrate 1 to form a bipolar transistor having a large current capacity.
    Type: Grant
    Filed: March 8, 2002
    Date of Patent: December 9, 2003
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Yoichi Tamaki, Takayuki Iwasaki, Kousuke Tsuji, Chiyoshi Kamada
  • Publication number: 20030169808
    Abstract: A communication system is provided including a transceiver and an application controller to transmit and receive signals through the transceiver. An isolator which insulates and separates the transceiver and application controller includes primary and secondary side circuits insulated from each other on a substrate and a capacitive insulating means to transfer signals between the primary and second sides while insulating and separating the primary side circuit from the secondary side circuit.
    Type: Application
    Filed: March 4, 2003
    Publication date: September 11, 2003
    Inventors: Seigoh Yukutake, Yasuyuki Kojima, Minehiro Nemoto, Masatsugu Amishiro, Takayuki Iwasaki, Shinichiro Mitani, Katsuhiro Furukawa, Chiyoshi Kamada, Atsuo Watanabe, Takayuki Oouchi, Nobuyasu Kanekawa
  • Publication number: 20030168099
    Abstract: A canister vent valve mounting structure for a canister vent valve is configured to prevent center deviation when the canister vent valve is connected to the canister and enables the canister to be shared by different vehicle models. The canister vent valve includes a connecting pipe part that fits into an insertion hole formed in the canister. Several mating projections are arranged in the circumferential direction of the connecting pipe part such that they are formed on the outside circumference of the connecting pipe part near the tip thereof. Several notches into which mating projections can be inserted are formed in the inside circumferential surface of the insertion hole. The canister vent valve mounting structure between the canister and the canister vent valve is configured and arranged to retain the canister vent valve in at least two different orientations relative to the canister.
    Type: Application
    Filed: February 14, 2003
    Publication date: September 11, 2003
    Applicant: Nissan Motor Co., Ltd.
    Inventors: Hideyuki Matsushima, Takayuki Iwasaki
  • Patent number: 6603807
    Abstract: An isolator is made monolithic by forming a capacitive insulating barrier using an interlayer insulation film on the semiconductor substrate to miniaturize the modem device by the monolithic isolator.
    Type: Grant
    Filed: February 26, 1999
    Date of Patent: August 5, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Seigoh Yukutake, Yasuyuki Kojima, Minehiro Nemoto, Masatsugu Amishiro, Takayuki Iwasaki, Shinichiro Mitani, Katsuhiro Furukawa, Chiyoshi Kamada, Atsuo Watanabe, Takayuki Oouchi, Nobuyasu Kanekawa
  • Publication number: 20020190285
    Abstract: The on-resistance per chip area of a horizontal power MOSFET is reduced. In the horizontal power MOSFET in accordance with the present invention, low resistance penetrating conductive zones penetrating from a semiconductor surface in a p-type semiconductor zone on a low resistance p-type semiconductor substrate connected to an outer source electrode up to the p-type semiconductor zone are formed, and two or more n-type drain zones electrically connected to drain electrodes are formed in a semiconductor zone surrounded by the low resistance penetrating conductive zones, and an outer drain zone is provided on an active zone.
    Type: Application
    Filed: July 3, 2002
    Publication date: December 19, 2002
    Inventors: Kozo Sakamoto, Eiji Yanokura, Masaki Shiraishi, Takayuki Iwasaki
  • Publication number: 20020179945
    Abstract: The on-resistance per chip area of a horizontal power MOSFET is reduced.
    Type: Application
    Filed: February 8, 2002
    Publication date: December 5, 2002
    Inventors: Kozo Sakamoto, Eiji Yanokura, Masaki Shiraishi, Takayuki Iwasaki
  • Patent number: 6476750
    Abstract: The hardware of an over-sampling A/D and D/A converter is provided, which hardware is capable of being operated with either kind of software: one corresponding to a first method in which the over-sampling ratio is fixed and the other corresponding to a second method in which the over-sampling ratio is variable. The value N3 written on the pseudo-frequency-dividing-ratio-register 11 and the value N4 written on the pseudo-over-sampling-ratio-register 21 are converted through a user interface into the frequency dividing ratio N1 by the conversion circuit 12 and the converted result is written in the frequency-dividing-ratio-register 10.
    Type: Grant
    Filed: February 9, 2000
    Date of Patent: November 5, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Nobuyasu Kanekawa, Yasuyuki Kojima, Seigou Yukutake, Minehiro Nemoto, Kazuhisa Takami, Takayuki Iwasaki, Yusuke Takeuchi, Katsuhiro Furukawa
  • Publication number: 20020149084
    Abstract: The number of design processes for fabricating semiconductor devices can be reduced by parallel connection of a plurality of unit bipolar transistors Qu that are completely electrically isolated from each other in a semiconductor layer of an SOI substrate 1 to form a bipolar transistor having a large current capacity.
    Type: Application
    Filed: March 8, 2002
    Publication date: October 17, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Yoichi Tamaki, Takayuki Iwasaki, Kousuke Tsuji, Chiyoshi Kamada
  • Publication number: 20020130369
    Abstract: The present invention provides a semiconductor integrated circuit device comprising a digital circuit and an analog circuit on a common substrate wherein a substrate effect constant of the analog circuit is at least less than a substrate effect constant of the digital circuit and wherein the analog circuit further comprises a P type polysilicon gate electrode for a nMOSFET and a N type polysilicon gate electrode for a pMOSFET.
    Type: Application
    Filed: August 10, 2001
    Publication date: September 19, 2002
    Inventors: Takayuki Iwasaki, Yusuke Takeuchi, Atsuo Watanabe
  • Patent number: 6384428
    Abstract: The present semiconductor switching device comprises a silicon carbide single crystal of hexagonal symmetry having a first conductive type and a semiconductor region of a second conductive type opposite to the first conductive type and locating in the silicon carbide single crystal. The silicon carbide single crystal of the first conductive type and the semiconductor region of the seconductive type form a pn junction. The pn junction interface has an interface extended in the depth direction from the surface of the silicon carbide single crystal, and the interface includes a crystal plane in parallel to the <1120> orientation of the silicon carbide single crystal or approximately in parallel thereto, thereby reducing the leak current.
    Type: Grant
    Filed: September 15, 2000
    Date of Patent: May 7, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Toshiyuki Oono, Takayuki Iwasaki, Tsutomu Yatsuo
  • Patent number: 6353236
    Abstract: A wide bandgap semiconductor single crystal is applied as a semiconductor substrate material of a semiconductor surge absorber, and a surge absorption operation starting voltage is set by a punchthrough of a pn junction, to obtain a semiconductor surge absorber with a repetitive operation and a high surge endurance.
    Type: Grant
    Filed: September 15, 1999
    Date of Patent: March 5, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Tsutomu Yatsuo, Takayuki Iwasaki, Hidekatsu Onose, Shin Kimura
  • Patent number: 6344809
    Abstract: In order to reduce the consumption of power of an isolator interface and an ADC, it is proposed to operate a calling signal reception or Caller ID signal reception function only with power supplied from the system switch while maintaining the on-hook condition of a telephone. At the time of normal operation, the output of the analogue digital converter is input to an isolator through the isolator interface, and at the time of the calling signal reception or the caller identification information reception, the output of the analogue digital converter is input directly to the isolator.
    Type: Grant
    Filed: November 3, 2000
    Date of Patent: February 5, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Nobuyasu Kanekawa, Yasuyuki Kojima, Seigou Yukutake, Minehiro Nemoto, Kazuhisa Takami, Takayuki Iwasaki, Yusuke Takeuchi, Yasuo Shima
  • Patent number: 6180959
    Abstract: In a silicon carbide static induction transistor, at a surface part of a semiconductor substrate, a p-type gate region is formed partially overlapping a n-type source region, whereby the high accuracy in alignment between the gate region and the source region is not required, and the gate withstand voltage can be highly increased since the substrate is made of silicon carbide, which improves the yield of static induction transistors.
    Type: Grant
    Filed: April 16, 1998
    Date of Patent: January 30, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Takayuki Iwasaki, Toshiyuki Ohno, Tsutomu Yatsuo
  • Patent number: 6169672
    Abstract: A power converting apparatus comprising a group of semiconductor switches and DC terminals electrically connected to the group of semiconductor switches, in which a clamping circuit is connected to the semiconductor switches or the DC terminals. Otherwise, a diode having a wide band gap is connected in parallel with a snubber diode or a snubber capacitor of a snubber circuit connected in parallel with the semiconductor switches. With such arrangement, an overvoltage or oscillating voltage impressed on the semiconductor switches is suppressed.
    Type: Grant
    Filed: December 23, 1998
    Date of Patent: January 2, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Shin Kimura, Tsutomu Yatsuo, Takayuki Iwasaki
  • Patent number: 6065319
    Abstract: Each of a pair of rolls has a barrel with different diameters axially of the barrel such that sum of the diameters of the barrels is substantially constant and that each of the rolls is bilaterally symmetrical. The rolls themselves have an ability to control workpiece profile and have at least one substantially parallel center portion.
    Type: Grant
    Filed: September 4, 1997
    Date of Patent: May 23, 2000
    Assignee: Ishikawajima-Harima Jukogyo Kabushiki Kaisha
    Inventors: Masao Mikami, Masahiro Kuchi, Sadahiko Shinya, Takayuki Iwasaki, Takashi Nishii
  • Patent number: 4642871
    Abstract: A manufacturing method of a clutch cover assembly comprising a first process in which an annular clutch cover body of a clutch cover is formed, a plurality of projections extending substantially radially inwardly from the inner periphery of the clutch cover body are formed and ends of said projections are bent so that the projections may extend in an axially inside direction of the clutch cover and toward a center of the clutch cover; a second process in which projection bodies between the clutch cover body and said projection ends are bent so that the projection bodies may extend in the axially inside direction of the clutch cover and toward the center of the clutch cover; and a third process in which a diaphragm spring and a pair of wire rings disposed at both sides of said spring for forming fulcrums for the spring are assembled to the projections, and then, the projection bodies are bent in a radially outward direction of the clutch cover and the projections ends are bent toward the inner peripheral porti
    Type: Grant
    Filed: May 29, 1985
    Date of Patent: February 17, 1987
    Assignee: Kabushiki Kaisha Daikin Seisakusho
    Inventors: Mamoru Ookubo, Takayuki Iwasaki, Kenji Mieda
  • Patent number: 4631795
    Abstract: A manufacturing method of a clutch cover assembly comprising an annular clutch cover provided with a plurality of projections, a diaphragm spring, and a pair of wire rings supported by said projections, characterized in that; said method comprises supporting the lower surface of the diaphragm spring, to which the wire rings have been assembled, by a lower die in such a position that said projections project upwardly from a body of the clutch cover; supporting radially inner sides of portions of said projection bodies positioned below the diaphragm spring by a projection body support provided in the lower die; downwardly bending the free ends of the projections, which incline upwardly from the projection bodies, to predetermined positions by an end pushing-down portion provided in the upper die; and supporting radially inner sides of portions of said projection bodies positioned above the diaphragm spring by a projection body support provided in the upper die.
    Type: Grant
    Filed: May 29, 1985
    Date of Patent: December 30, 1986
    Assignee: Kabushiki Kaisha Daikin Seisakusho
    Inventors: Mamoru Ookubo, Takayuki Iwasaki, Kenji Mieda