Patents by Inventor Takayuki Kawahara

Takayuki Kawahara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8508283
    Abstract: Back-gate voltage control provides a high speed and low power consumption LSI operable in a wide temperature range in which a MOS transistor having back gates is used specifically according to operating characteristics of a circuit. In the LSI, an FD-SOI structure having an embedded oxide film layer is used and a lower semiconductor region of the embedded oxide film layer is used as a back gate. A voltage for back gates in logic circuits having a small load in logic circuit block is controlled in response to activation of the block from outside of the block. Transistors, in which the gate and the back gate are connected to each other, are used for the circuit generating the back gate driving signal, and logic circuits having a heavy load such as circuit block output section, and the back gates are directly controlled according to a gate input signal.
    Type: Grant
    Filed: April 6, 2011
    Date of Patent: August 13, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Takayuki Kawahara, Masanao Yamaoka
  • Publication number: 20130105760
    Abstract: For example, one memory cell is configured using two memory cell transistors and one phase change element by disposing a plurality of diffusion layers in parallel to a bit-line, disposing gates between the diffusion layers so as to cross the bit-line, disposing bit-line contacts and source contacts alternately to the plurality of diffusion layers arranged in a bit-line direction for each diffusion layer, and providing a phase change element on the source contact. Also, the phase change element can be provided on the bit-line contact instead of the source contact. By this means, for example, increase in drivability of the memory cell transistors and reduction in area can be realized.
    Type: Application
    Filed: December 19, 2012
    Publication date: May 2, 2013
    Applicant: Renesas Electronics Corporation
    Inventors: Riichiro TAKEMURA, Kenzo KUROTSUCHI, Takayuki KAWAHARA
  • Patent number: 8427864
    Abstract: To write information on a memory cell of SPRAM formed of an MOS transistor and a tunnel magnetoresistive element, the memory cell is supplied with a current in a direction opposite to a direction of a current required for writing the information on the memory cell, and then, the memory cell is supplied with a current required for writing. In this manner, even when the same information is sequentially written on the memory cell, since the currents in the two directions are caused to flow in pairs in the tunnel magnetoresistive element of the memory cell each time information is rewritten, deterioration of a film that forms the tunnel magnetoresistive element can be suppressed. Therefore, reliability of the SPRAM can be improved.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: April 23, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Takayuki Kawahara, Kiyoo Itoh, Riichiro Takemura, Kenchi Ito
  • Publication number: 20130051134
    Abstract: The disclosed semiconductor recording device achieves multi-valued reading and writing using a spin-injection magnetization-reversal tunneling magnetoresistive element (TMR element). A first current that has at least the same value as that of the element requiring the highest current to reverse the magnetization thereof among a plurality of TMR elements is, in the direction that causes reversal to either a parallel state or an anti-parallel state, applied to a memory cell having the plurality of TMR elements, and then a second current which is in the reverse direction from the first current and of which only the value needed to reverse the magnetoresistance state of at least one TMR element excluding the element requiring the maximum current among the plurality of TMR elements is applied to each, and multi-valued writing is performed.
    Type: Application
    Filed: April 5, 2011
    Publication date: February 28, 2013
    Inventors: Takayuki Kawahara, Riichiro Takemura, Takashi Ishigaki, Kiyoo Itoh
  • Publication number: 20130044537
    Abstract: There is provided a magnetic memory with using a magnetoresistive effect element of a spin-injection magnetization reversal type, in which a multi-value operation is possible and whose manufacturing and operation are simple. A preferred aim of this is solved by providing two or more magnetoresistive effect elements which are electrically connected in series to each other and by selecting one of the series-connected elements depending on a direction of a current carried in the series-connected elements, a magnitude thereof, and an order of the current thereof for performing the writing operation. For example, it is solved by differentiating plane area sizes of the respective magnetoresistive effect elements which have the same film structure from each other so as to differentiate resistance change amounts caused by respective magnetization reversal and threshold current values required for respective magnetization reversal from each other.
    Type: Application
    Filed: January 13, 2011
    Publication date: February 21, 2013
    Inventors: Takashi Ishigaki, Takayuki Kawahara, Riichiro Takemura, Kazuo Ono, Kenchi Ito
  • Publication number: 20130033928
    Abstract: Since a nonvolatile RAM allows random reading and writing operations, an erasing mode is unnecessary. From the system side, however, it is desirable to have the erasing mode because of its nonvolatile characteristic. Moreover, the erasing operation is desirably carried out at high speed with low power consumption. Therefore, memory cell arrays COA and DTA containing a plurality of memory cells MC each having a magnetoresistive element are provided, a series of data is written to the memory cell arrays COA and DTA, and at the time of erasing, an erasing operation is carried out by writing predetermined data only to the memory cell array COA.
    Type: Application
    Filed: February 2, 2010
    Publication date: February 7, 2013
    Inventors: Takayuki Kawahara, Riichiro Takemura, Kazuo Ono, Nobuaki Kohinata
  • Patent number: 8363464
    Abstract: For example, one memory cell is configured using two memory cell transistors and one phase change element by disposing a plurality of diffusion layers in parallel to a bit-line, disposing gates between the diffusion layers so as to cross the bit-line, disposing bit-line contacts and source contacts alternately to the plurality of diffusion layers arranged in a bit-line direction for each diffusion layer, and providing a phase change element on the source contact. Also, the phase change element can be provided on the bit-line contact instead of the source contact. By this means, for example, increase in drivability of the memory cell transistors and reduction in area can be realized.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: January 29, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Riichiro Takemura, Kenzo Kurotsuchi, Takayuki Kawahara
  • Patent number: 8330496
    Abstract: An object of the present invention is to provide a technique of reducing the leakage current of a drive circuit for driving a circuit that must retain a potential (or information) when in its standby state. A semiconductor integrated circuit device of the present invention includes a drive circuit for driving a circuit block. This drive circuit is made up of a double gate transistor with gates having different gate oxide film thicknesses. When the circuit block is in its standby state, the gate of the double gate transistor having a thinner gate oxide film is turned off and that having a thicker gate oxide film is turned on. This arrangement allows a reduction in the leakage currents of both the circuit block and the drive circuit while allowing the drive circuit to deliver or cut off power to the circuit block.
    Type: Grant
    Filed: November 18, 2009
    Date of Patent: December 11, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Masanao Yamaoka, Takayuki Kawahara
  • Publication number: 20120256157
    Abstract: For example, one memory cell is configured using two memory cell transistors and one phase change element by disposing a plurality of diffusion layers in parallel to a bit-line, disposing gates between the diffusion layers so as to cross the bit-line, disposing bit-line contacts and source contacts alternately to the plurality of diffusion layers arranged in a bit-line direction for each diffusion layer, and providing a phase change element on the source contact. Also, the phase change element can be provided on the bit-line contact instead of the source contact. By this means, for example, increase in drivability of the memory cell transistors and reduction in area can be realized.
    Type: Application
    Filed: June 20, 2012
    Publication date: October 11, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Riichiro TAKEMURA, Kenzo KUROTSUCHI, Takayuki KAWAHARA
  • Patent number: 8228724
    Abstract: For example, one memory cell is configured using two memory cell transistors and one phase change element by disposing a plurality of diffusion layers in parallel to a bit-line, disposing gates between the diffusion layers so as to cross the bit-line, disposing bit-line contacts and source contacts alternately to the plurality of diffusion layers arranged in a bit-line direction for each diffusion layer, and providing a phase change element on the source contact. Also, the phase change element can be provided on the bit-line contact instead of the source contact. By this means, for example, increase in drivability of the memory cell transistors and reduction in area can be realized.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: July 24, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Riichiro Takemura, Kenzo Kurotsuchi, Takayuki Kawahara
  • Patent number: 8203868
    Abstract: An object of the present invention is to provide a technique of reducing the power consumption of an entire low power consumption SRAM LSI circuit employing scaled-down transistors and of increasing the stability of read and write operations on the memory cells by reducing the subthreshold leakage current and the leakage current flowing from the drain electrode to the substrate electrode. Another object of the present invention is to provide a technique of preventing an increase in the number of transistors in a memory cell and thereby preventing an increase in the cell area. Still another object of the present invention is to provide a technique of ensuring stable operation of an SRAM memory cell made up of SOI or FD-SOI transistors having a BOX layer by controlling the potentials of the wells under the BOX layers of the drive transistors.
    Type: Grant
    Filed: February 4, 2011
    Date of Patent: June 19, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Masanao Yamaoka, Takayuki Kawahara
  • Patent number: 8199596
    Abstract: A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pull-down circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.
    Type: Grant
    Filed: November 3, 2010
    Date of Patent: June 12, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Satoru Akiyama, Riichiro Takemura, Takayuki Kawahara, Tomonori Sekiguchi
  • Publication number: 20120097912
    Abstract: For example, one memory cell is configured using two memory cell transistors and one phase change element by disposing a plurality of diffusion layers in parallel to a bit-line, disposing gates between the diffusion layers so as to cross the bit-line, disposing bit-line contacts and source contacts alternately to the plurality of diffusion layers arranged in a bit-line direction for each diffusion layer, and providing a phase change element on the source contact. Also, the phase change element can be provided on the bit-line contact instead of the source contact. By this means, for example, increase in drivability of the memory cell transistors and reduction in area can be realized.
    Type: Application
    Filed: January 6, 2012
    Publication date: April 26, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Riichiro TAKEMURA, Kenzo KUROTSUCHI, Takayuki KAWAHARA
  • Publication number: 20120081952
    Abstract: To write information on a memory cell of SPRAM formed of an MOS transistor and a tunnel magnetoresistive element, the memory cell is supplied with a current in a direction opposite to a direction of a current required for writing the information on the memory cell, and then, the memory cell is supplied with a current required for writing. In this manner, even when the same information is sequentially written on the memory cell, since the currents in the two directions are caused to flow in pairs in the tunnel magnetoresistive element of the memory cell each time information is rewritten, deterioration of a film that forms the tunnel magnetoresistive element can be suppressed. Therefore, reliability of the SPRAM can be improved.
    Type: Application
    Filed: June 2, 2010
    Publication date: April 5, 2012
    Inventors: Takayuki Kawahara, Kiyoo Itoh, Riichiro Takemura, Kenchi Ito
  • Patent number: 8116128
    Abstract: For example, one memory cell is configured using two memory cell transistors and one phase change element by disposing a plurality of diffusion layers in parallel to a bit-line, disposing gates between the diffusion layers so as to cross the bit-line, disposing bit-line contacts and source contacts alternately to the plurality of diffusion layers arranged in a bit-line direction for each diffusion layer, and providing a phase change element on the source contact. Also, the phase change element can be provided on the bit-line contact instead of the source contact. By this means, for example, increase in drivability of the memory cell transistors and reduction in area can be realized.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: February 14, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Riichiro Takemura, Kenzo Kurotsuchi, Takayuki Kawahara
  • Patent number: 8031511
    Abstract: At the time of, for example, a set operation (SET) for making a phase-change element in a crystalline state, a pulse of a voltage Vreset required for melting the element is applied to the phase-change element, and subsequently a pulse of a voltage Vset that is lower than Vreset and is required for crystallizing the element is applied thereto. And, the magnitude of this voltage Vset is then changed depending on the ambient temperature so that the magnitude of the voltage Vset is small as the temperature becomes high (TH). In this manner, a margin of a write operation between the set operation and a reset operation (RESET) for making the element to be in amorphous state is improved.
    Type: Grant
    Filed: February 9, 2011
    Date of Patent: October 4, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Kenichi Osada, Naoki Kitai, Takayuki Kawahara, Kazumasa Yanagisawa
  • Publication number: 20110194361
    Abstract: An array configuration capable of supplying a necessary and sufficient current in a small area is achieved and a reference cell configuration suitable to temperature characteristics of a TMR element is achieved. In a memory using inversion of spin transfer switching, a plurality of program drivers are arranged separately along one global bit line, and one sense amplifier is provided to one global bit line. A reference cell to which “1” and “0” are programmed is shared by two arrays and a sense amplifier.
    Type: Application
    Filed: October 5, 2009
    Publication date: August 11, 2011
    Inventors: Takayuki Kawahara, Riichiro Takemura, Kazuo Ono
  • Patent number: 7995377
    Abstract: An object of the present invention is to provide a technique of reducing the power consumption of an entire low power consumption SRAM LSI circuit employing scaled-down transistors and of increasing the stability of read and write operations on the memory cells by reducing the subthreshold leakage current and the leakage current flowing from the drain electrode to the substrate electrode. Another object of the present invention is to provide a technique of preventing an increase in the number of transistors in a memory cell and thereby preventing an increase in the cell area. Still another object of the present invention is to provide a technique of ensuring stable operation of an SRAM memory cell made up of SOI or FD-SOI transistors having a BOX layer by controlling the potentials of the wells under the BOX layers of the drive transistors.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: August 9, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Masanao Yamaoka, Takayuki Kawahara
  • Publication number: 20110188329
    Abstract: The semiconductor integrated circuit (1) has a memory (4) and a logic circuit (5), which are mixedly palletized on a silicon substrate (2). The memory includes a partially-depleted type nMOS (6) having an SOI structure and formed on UTB (3). The partially-depleted type nMOS has a backgate region (14) under UTB, to which a voltage can be applied independently of a corresponding gate terminal. The logic circuit includes an nMOS (7) and a pMOS (8), and both are of a fully-depleted type, formed on UTB and have an SOI structure.
    Type: Application
    Filed: April 13, 2011
    Publication date: August 4, 2011
    Inventors: Takayuki Kawahara, Masanao Yamaoka, Nobuyuki Sugii
  • Publication number: 20110181319
    Abstract: The present invention provides a high speed and low power consumption LSI operable in a wide temperature range in which a MOS transistor having back gates is used specifically according to operating characteristics of a circuit. In the LSI, an FD-SOI structure having an embedded oxide film layer is used and a lower semiconductor region of the embedded oxide film layer is used as a back gate. A voltage for back gates in the logic circuits having a small load in the logic circuit block is controlled in response to activation of the block from outside of the block. Transistors, in which the gate and the back gate are connected to each other, are used for the circuit generating the back gate driving signal, and logic circuits having a heavy load such as circuit block output section, and the back gates are directly controlled according to the gate input signal.
    Type: Application
    Filed: April 6, 2011
    Publication date: July 28, 2011
    Inventors: Takayuki KAWAHARA, Masanao YAMAOKA