Patents by Inventor Takehiko Maeda

Takehiko Maeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11270971
    Abstract: A semiconductor device capable of suppressing propagation of a crack caused by a temperature cycle at a bonding part between a bonding pad and a bonding wire is provided. A semiconductor device according to an embodiment includes a semiconductor chip having bonding pads and bonding wires. The bonding pad includes a barrier layer and a bonding layer formed on the barrier layer and formed of a material containing aluminum. The bonding wire is bonded to the bonding pad and formed of a material containing copper. An intermetallic compound layer formed of an intermetallic compound containing copper and aluminum is formed so as to reach the barrier layer from the bonding wire in at least a part of the bonding part between the bonding pad and the bonding wire.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: March 8, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kenji Ikura, Hideki Ishii, Takehiko Maeda, Takeumi Kato
  • Patent number: 10895373
    Abstract: A light projection device includes a tubular casing having a light-emitting part at one tube end; a light source configured with a light-emitting diode; and a light amount control mechanism positioned between the light source and the light-emitting part. The light amount control mechanism includes a rotating body, an operating part attached to the rotating body such as to allow for rotary operation of the rotating body from outside the casing, a variable resistor, and a link mechanism operably connecting the rotating body and the variable resistor such that a forward movement of the rotating body causes a movable part of the variable resistor to move in a direction in which the amount of current is increased and such that a backward movement of the rotating body causes the movable part of the variable resistor to move in a direction in which the amount of current is decreased.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: January 19, 2021
    Assignee: Ushio Lighting, Inc.
    Inventor: Takehiko Maeda
  • Publication number: 20200408393
    Abstract: A light projection device includes a tubular casing having a light-emitting part at one tube end; a light source configured with a light-emitting diode; and a light amount control mechanism positioned between the light source and the light-emitting part. The light amount control mechanism includes a rotating body, an operating part attached to the rotating body such as to allow for rotary operation of the rotating body from outside the casing, a variable resistor, and a link mechanism operably connecting the rotating body and the variable resistor such that a forward movement of the rotating body causes a movable part of the variable resistor to move in a direction in which the amount of current is increased and such that a backward movement of the rotating body causes the movable part of the variable resistor to move in a direction in which the amount of current is decreased.
    Type: Application
    Filed: December 20, 2018
    Publication date: December 31, 2020
    Applicant: Ushio Lighting, Inc.
    Inventor: Takehiko MAEDA
  • Publication number: 20200135687
    Abstract: A semiconductor device capable of suppressing propagation of a crack caused by a temperature cycle at a bonding part between a bonding pad and a bonding wire is provided. A semiconductor device according to an embodiment includes a semiconductor chip having bonding pads and bonding wires. The bonding pad includes a barrier layer and a bonding layer formed on the barrier layer and formed of a material containing aluminum. The bonding wire is bonded to the bonding pad and formed of a material containing copper. An intermetallic compound layer formed of an intermetallic compound containing copper and aluminum is formed so as to reach the barrier layer from the bonding wire in at least a part of the bonding part between the bonding pad and the bonding wire.
    Type: Application
    Filed: September 19, 2019
    Publication date: April 30, 2020
    Inventors: Kenji IKURA, Hideki ISHII, Takehiko MAEDA, Takeumi KATO
  • Patent number: 10181450
    Abstract: A pad formed in a semiconductor chip is formed such that a thickness of an aluminum film in a wire bonding portion is smaller than that of an aluminum film in a peripheral portion covered with a protective film. On the other hand, a thickness of a wiring formed in the same step as the pad is larger than that of the pad in the wire bonding portion. The main conductive film of the pad in the wire bonding portion is comprised of only one layer of a first aluminum film, while the main conductive film of the wiring is comprised of at least two layers of aluminum films (the first aluminum film and a second aluminum film) in any region of the wiring.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: January 15, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Seiya Isozaki, Takashi Moriyama, Takehiko Maeda
  • Publication number: 20180068964
    Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate, forming, over a main surface the semiconductor substrate, a first insulating film, forming, over the first insulating film, an Al-containing conductive film containing aluminum as a main component, patterning the Al-containing conductive film to form a pad, forming, over the first insulating film, a second insulating film to cover the pad therewith, forming an opening in the second insulating film, and electrically coupling a copper wire to the pad exposed from the opening.
    Type: Application
    Filed: October 31, 2017
    Publication date: March 8, 2018
    Inventors: Takehiko MAEDA, Akira Yajima, Satoshi Itou, Fumiyoshi Kawashiro
  • Patent number: 9853005
    Abstract: An improvement is achieved in the reliability of a semiconductor device. Over a semiconductor substrate, an interlayer insulating film is formed and, over the interlayer insulating film, a pad is formed. Over the interlayer insulating film, an insulating film is formed so as to cover the pad. In the insulating film, an opening is formed to expose a part of the pad. The pad is a pad to which a copper wire is to be electrically coupled and which includes an Al-containing conductive film containing aluminum as a main component. Over the Al-containing conductive film in a region overlapping the opening in plan view, a laminated film including a barrier conductor film, and a metal film over the barrier conductor film is formed. The metal film is in an uppermost layer. The barrier conductor film is a single-layer film or a laminated film including one or more layers of films selected from the group consisting of a Ti film, a TiN film, a Ta film, a TaN film, a W film, a WN film, a TiW film, and a TaW film.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: December 26, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takehiko Maeda, Akira Yajima, Satoshi Itou, Fumiyoshi Kawashiro
  • Publication number: 20170287868
    Abstract: A pad formed in a semiconductor chip is formed such that a thickness of an aluminum film in a wire bonding portion is smaller than that of an aluminum film in a peripheral portion covered with a protective film. On the other hand, a thickness of a wiring formed in the same step as the pad is larger than that of the pad in the wire bonding portion. The main conductive film of the pad in the wire bonding portion is comprised of only one layer of a first aluminum film, while the main conductive film of the wiring is comprised of at least two layers of aluminum films (the first aluminum film and a second aluminum film) in any region of the wiring.
    Type: Application
    Filed: February 1, 2017
    Publication date: October 5, 2017
    Inventors: Seiya ISOZAKI, Takashi MORIYAMA, Takehiko MAEDA
  • Patent number: 9659888
    Abstract: Even when a thermal stress is applied to an electrode pad, the electrode pad is prevented from being moved. A substrate of a semiconductor chip has a rectangular planar shape. The semiconductor chip has a plurality of electrode pads. The center of a first electrode pad is positioned closer to the end of a first side in the direction along the first side of the substrate as compared to the center of a first opening. Thus, in a part of the first electrode pad covered with an insulating film, a width of the part closer to the end of the first side in the direction along the first side is larger than another width of the part opposite to the above-mentioned width.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: May 23, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Makio Okada, Takehiko Maeda
  • Publication number: 20160163667
    Abstract: Even when a thermal stress is applied to an electrode pad, the electrode pad is prevented from being moved. A substrate of a semiconductor chip has a rectangular planar shape. The semiconductor chip has a plurality of electrode pads. The center of a first electrode pad is positioned closer to the end of a first side in the direction along the first side of the substrate as compared to the center of a first opening. Thus, in a part of the first electrode pad covered with an insulating film, a width of the part closer to the end of the first side in the direction along the first side is larger than another width of the part opposite to the above-mentioned width.
    Type: Application
    Filed: February 12, 2016
    Publication date: June 9, 2016
    Inventors: Makio Okada, Takehiko Maeda
  • Patent number: 9299632
    Abstract: Even when a thermal stress is applied to an electrode pad, the electrode pad is prevented from being moved. A substrate of a semiconductor chip has a rectangular planar shape. The semiconductor chip has a plurality of electrode pads. The center of a first electrode pad is positioned closer to the end of a first side in the direction along the first side of the substrate as compared to the center of a first opening. Thus, in a part of the first electrode pad covered with an insulating film, a width of the part closer to the end of the first side in the direction along the first side is larger than another width of the part opposite to the above-mentioned width.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: March 29, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Makio Okada, Takehiko Maeda
  • Publication number: 20160013142
    Abstract: An improvement is achieved in the reliability of a semiconductor device. Over a semiconductor substrate, an interlayer insulating film is formed and, over the interlayer insulating film, a pad is formed. Over the interlayer insulating film, an insulating film is formed so as to cover the pad. In the insulating film, an opening is formed to expose a part of the pad. The pad is a pad to which a copper wire is to be electrically coupled and which includes an Al-containing conductive film containing aluminum as a main component. Over the Al-containing conductive film in a region overlapping the opening in plan view, a laminated film including a barrier conductor film, and a metal film over the barrier conductor film is formed. The metal film is in an uppermost layer. The barrier conductor film is a single-layer film or a laminated film including one or more layers of films selected from the group consisting of a Ti film, a TiN film, a Ta film, a TaN film, a W film, a WN film, a TiW film, and a TaW film.
    Type: Application
    Filed: July 6, 2015
    Publication date: January 14, 2016
    Inventors: Takehiko MAEDA, Akira YAJIMA, Satoshi ITOU, Fumiyoshi KAWASHIRO
  • Patent number: 8975150
    Abstract: A transparent board is positioned on a support board provided with a positioning mark, and a release material is provided. A semiconductor element is then positioned so that the electrode element faces upward, and the support board is then removed. An insulating resin is then formed on the release material so as to cover the semiconductor element; and a via, a wiring layer, an insulation layer, an external terminal, and a solder resist are then formed. The transparent board is then peeled from the semiconductor device through the use of the release material. A chip can thereby be mounted with high precision, there is no need to provide a positioning mark during mounting of the chip on the substrate in the manufacturing process, and the substrate can easily be removed. As a result, a semiconductor device having high density and a thin profile can be manufactured at low cost.
    Type: Grant
    Filed: July 25, 2011
    Date of Patent: March 10, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Kentaro Mori, Shintaro Yamamichi, Hideya Murai, Takuo Funaya, Masaya Kawano, Takehiko Maeda, Kouji Soejima
  • Publication number: 20150061159
    Abstract: Even when a thermal stress is applied to an electrode pad, the electrode pad is prevented from being moved. A substrate of a semiconductor chip has a rectangular planar shape. The semiconductor chip has a plurality of electrode pads. The center of a first electrode pad is positioned closer to the end of a first side in the direction along the first side of the substrate as compared to the center of a first opening. Thus, in a part of the first electrode pad covered with an insulating film, a width of the part closer to the end of the first side in the direction along the first side is larger than another width of the part opposite to the above-mentioned width.
    Type: Application
    Filed: August 14, 2014
    Publication date: March 5, 2015
    Inventors: Makio Okada, Takehiko Maeda
  • Patent number: 8536691
    Abstract: A semiconductor device including a metal frame having a penetrating opening; a semiconductor chip provided in the opening; an insulating layer provided on the upper surface of the metal frame such that the insulating layer covers the upper surface, which is the circuit-formed surface of the semiconductor chip; an interconnect layer provided only on the upper-surface side of the metal frame with intervention of the insulating material and electrically connected to a circuit of the semiconductor chip; a via conductor provided on the upper surface of said semiconductor chip to electrically connect the circuit of the semiconductor chip and the interconnect layer; and a resin layer provided on the lower surface of the metal frame.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: September 17, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Katsumi Kikuchi, Shintaro Yamamichi, Hideya Murai, Katsumi Maeda, Takuo Funaya, Kentaro Mori, Takehiko Maeda, Masaya Kawano, Yuuji Kayashima
  • Patent number: 8389414
    Abstract: A wiring board has an insulating layer, a plurality of wiring layers formed in such a way as to be insulated from each other by the insulating layer, and a plurality of vias formed in the insulating layer to connect the wiring layers. Of the wiring layers, a surface wiring layer formed in one surface of the insulating layer include a first metal film exposed from the one surface and a second metal film embedded in the insulating layer and stacked on the first metal film. Edges of the first metal film project from edges of the second metal film in the direction in which the second metal film spreads. By designing the shape of the wiring layers embedded in the insulating layer in this manner, it is possible to obtain a highly reliable wiring board that can be effectively prevented from side etching in the manufacturing process and can adapt to miniaturization and highly dense packaging of wires.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: March 5, 2013
    Assignees: NEC Corporation, Renesas Electronics Corporation
    Inventors: Katsumi Kikuchi, Shintaro Yamamichi, Hideya Murai, Takuo Funaya, Kentaro Mori, Takehiko Maeda, Hirokazu Honda, Kenta Ogawa, Jun Tsukano
  • Publication number: 20130005090
    Abstract: A semiconductor device manufacturing method includes cutting a resin sealing body into a plurality of pieces, the resin sealing body including a plurality of semiconductor chips mounted on a wiring board, a heat spreader disposed above the plurality of the semiconductor chips, and a sealing resin filled between the wiring board and the heat spreader, wherein the cutting the resin sealing body includes shaving the resin sealing body from a side of the heat spreader, and shaving the resin sealing body from a side of the wiring board, wherein the shaving the resin sealing body from the side of the wiring board is carried out after the shaving from the side of the heat spreader, and wherein the resin sealing body is completely cut off by the shaving from the side of the wiring board, and mounting a group of ball-like electrodes at a back side of the wiring board.
    Type: Application
    Filed: September 11, 2012
    Publication date: January 3, 2013
    Inventors: Yuko Sato, Takehiko Maeda, Fumiyoshi Kawashiro
  • Publication number: 20110281401
    Abstract: A transparent board is positioned on a support board provided with a positioning mark, and a release material is provided. A semiconductor element is then positioned so that the electrode element faces upward, and the support board is then removed. An insulating resin is then formed on the release material so as to cover the semiconductor element; and a via, a wiring layer, an insulation layer, an external terminal, and a solder resist are then formed. The transparent board is then peeled from the semiconductor device through the use of the release material. A chip can thereby be mounted with high precision, there is no need to provide a positioning mark during mounting of the chip on the substrate in the manufacturing process, and the substrate can easily be removed. As a result, a semiconductor device having high density and a thin profile can be manufactured at low cost.
    Type: Application
    Filed: July 25, 2011
    Publication date: November 17, 2011
    Applicants: C/O RENESAS ELECTRONICS CORPORATION, NEC CORPORATION
    Inventors: Kentaro MORI, Shintaro YAMAMICHI, Hideya MURAI, Takuo FUNAYA, Masaya KAWANO, Takehiko MAEDA, Kouji SOEJIMA
  • Patent number: 8043953
    Abstract: A semiconductor device that can be readily manufactured, can include a large number of pads, and can be thin, and a method for manufacturing the same are provided. The semiconductor device is characterized in that the semiconductor device includes an LSI chip, an insulating layer provided on the LSI chip and made of a nonphotosensitive resin, the insulating layer including a via hole in the position corresponding to an externally connected pad, and a wiring layer extending along the insulating layer through the via hole to the externally connected pad, and at least part of the via hole is formed by irradiating the insulating layer with laser light.
    Type: Grant
    Filed: January 15, 2008
    Date of Patent: October 25, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Hideya Murai, Yuji Kayashima, Takehiko Maeda, Shintaro Yamamichi, Takuo Funaya
  • Patent number: 8035217
    Abstract: A transparent board is positioned on a support board provided with a positioning mark, and a release material is provided. A semiconductor element is then positioned so that the electrode element faces upward, and the support board is then removed. An insulating resin is then formed on the release material so as to cover the semiconductor element; and a via, a wiring layer, an insulation layer, an external terminal, and a solder resist are then formed. The transparent board is then peeled from the semiconductor device through the use of the release material. A chip can thereby be mounted with high precision, there is no need to provide a positioning mark during mounting of the chip on the substrate in the manufacturing process, and the substrate can easily be removed. As a result, a semiconductor device having high density and a thin profile can be manufactured at low cost.
    Type: Grant
    Filed: June 9, 2008
    Date of Patent: October 11, 2011
    Assignees: NEC Corporation, Renesas Electronics Corporation
    Inventors: Kentaro Mori, Shintaro Yamamichi, Hideya Murai, Takuo Funaya, Masaya Kawano, Takehiko Maeda, Kouji Soejima