Patents by Inventor Takehiko Maeda

Takehiko Maeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110281401
    Abstract: A transparent board is positioned on a support board provided with a positioning mark, and a release material is provided. A semiconductor element is then positioned so that the electrode element faces upward, and the support board is then removed. An insulating resin is then formed on the release material so as to cover the semiconductor element; and a via, a wiring layer, an insulation layer, an external terminal, and a solder resist are then formed. The transparent board is then peeled from the semiconductor device through the use of the release material. A chip can thereby be mounted with high precision, there is no need to provide a positioning mark during mounting of the chip on the substrate in the manufacturing process, and the substrate can easily be removed. As a result, a semiconductor device having high density and a thin profile can be manufactured at low cost.
    Type: Application
    Filed: July 25, 2011
    Publication date: November 17, 2011
    Applicants: C/O RENESAS ELECTRONICS CORPORATION, NEC CORPORATION
    Inventors: Kentaro MORI, Shintaro YAMAMICHI, Hideya MURAI, Takuo FUNAYA, Masaya KAWANO, Takehiko MAEDA, Kouji SOEJIMA
  • Patent number: 8043953
    Abstract: A semiconductor device that can be readily manufactured, can include a large number of pads, and can be thin, and a method for manufacturing the same are provided. The semiconductor device is characterized in that the semiconductor device includes an LSI chip, an insulating layer provided on the LSI chip and made of a nonphotosensitive resin, the insulating layer including a via hole in the position corresponding to an externally connected pad, and a wiring layer extending along the insulating layer through the via hole to the externally connected pad, and at least part of the via hole is formed by irradiating the insulating layer with laser light.
    Type: Grant
    Filed: January 15, 2008
    Date of Patent: October 25, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Hideya Murai, Yuji Kayashima, Takehiko Maeda, Shintaro Yamamichi, Takuo Funaya
  • Patent number: 8035217
    Abstract: A transparent board is positioned on a support board provided with a positioning mark, and a release material is provided. A semiconductor element is then positioned so that the electrode element faces upward, and the support board is then removed. An insulating resin is then formed on the release material so as to cover the semiconductor element; and a via, a wiring layer, an insulation layer, an external terminal, and a solder resist are then formed. The transparent board is then peeled from the semiconductor device through the use of the release material. A chip can thereby be mounted with high precision, there is no need to provide a positioning mark during mounting of the chip on the substrate in the manufacturing process, and the substrate can easily be removed. As a result, a semiconductor device having high density and a thin profile can be manufactured at low cost.
    Type: Grant
    Filed: June 9, 2008
    Date of Patent: October 11, 2011
    Assignees: NEC Corporation, Renesas Electronics Corporation
    Inventors: Kentaro Mori, Shintaro Yamamichi, Hideya Murai, Takuo Funaya, Masaya Kawano, Takehiko Maeda, Kouji Soejima
  • Patent number: 7999401
    Abstract: Semiconductor device has a semiconductor chip embedded in an insulating layer. A semiconductor device comprises a semiconductor chip formed to have external connection pads and a positioning mark that is for via formation; an insulating layer containing a non-photosensitive resin as an ingredient and having a plurality of vias; and wiring electrically connected to the external connection pads through the vias and at least a portion of which is formed on the insulating layer. The insulating layer is formed to have a recess in a portion above the positioning mark. The bottom of the recess is the insulating layer alone. Vias have high positional accuracy relative to the mark.
    Type: Grant
    Filed: July 24, 2008
    Date of Patent: August 16, 2011
    Assignees: NEC Corporation, Renesas Electronics Corporation
    Inventors: Hideya Murai, Kentaro Mori, Shintaro Yamamichi, Masaya Kawano, Takehiko Maeda, Kouji Soejima
  • Publication number: 20110136298
    Abstract: A wiring board has an insulating layer, a plurality of wiring layers formed in such a way as to be insulated from each other by the insulating layer, and a plurality of vias formed in the insulating layer to connect the wiring layers. Of the wiring layers, a surface wiring layer formed in one surface of the insulating layer include a first metal film exposed from the one surface and a second metal film embedded in the insulating layer and stacked on the first metal film. Edges of the first metal film project from edges of the second metal film in the direction in which the second metal film spreads. By designing the shape of the wiring layers embedded in the insulating layer in this manner, it is possible to obtain a highly reliable wiring board that can be effectively prevented from side etching in the manufacturing process and can adapt to miniaturization and highly dense packaging of wires.
    Type: Application
    Filed: February 14, 2011
    Publication date: June 9, 2011
    Applicants: NEC CORPORATION, RENESAS ELECTRONICS CORPORATION
    Inventors: Katsumi KIKUCHI, Shintaro YAMAMICHI, Hideya MURAI, Takuo FUNAYA, Kentaro MORI, Takehiko MAEDA, Hirokazu HONDA, Kenta OGAWA, Jun TSUKANO
  • Publication number: 20110104872
    Abstract: A semiconductor device manufacturing method includes cutting a resin sealing body into a plurality of pieces, in which the resin sealing body includes a plurality of semiconductor chips mounted on a wiring board, a heat spreader disposed above the plurality of the semiconductor chips, and a sealing resin filled between the wiring board and the heat spreader. The cutting the resin sealing body includes shaving the resin sealing body from a side of the heat spreader, and shaving the resin sealing body from a side of the wiring board. The shaving the resin sealing body from the side of the heat spreader includes etching the heat spreader.
    Type: Application
    Filed: January 12, 2011
    Publication date: May 5, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuko Sato, Takehiko Maeda, Fumiyoshi Kawashiro
  • Patent number: 7911038
    Abstract: A wiring board has an insulating layer, a plurality of wiring layers formed in such a way as to be insulated from each other by the insulating layer, and a plurality of vias formed in the insulating layer to connect the wiring layers. Of the wiring layers, a surface wiring layer formed in one surface of the insulating layer include a first metal film exposed from the one surface and a second metal film embedded in the insulating layer and stacked on the first metal film. Edges of the first metal film project from edges of the second metal film in the direction in which the second metal film spreads. By designing the shape of the wiring layers embedded in the insulating layer in this manner, it is possible to obtain a highly reliable wiring board that can be effectively prevented from side etching in the manufacturing process and can adapt to miniaturization and highly dense packaging of wires.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: March 22, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Katsumi Kikuchi, Shintaro Yamamichi, Hideya Murai, Takuo Funaya, Kentaro Mori, Takehiko Maeda, Hirokazu Honda, Kenta Ogawa, Jun Tsukano
  • Patent number: 7838779
    Abstract: A wiring board in which lower-layer wiring composed of a wiring body and an etching barrier layer is formed in a concave portion formed on one face of a board-insulating film, upper-layer wiring is formed on the other face of the board-insulating film, and the upper-layer wiring and the wiring body of the lower-layer wiring are connected to each other through a via hole formed in the board-insulating film. The via hole is barrel-shaped, bell-shaped, or bellows-shaped.
    Type: Grant
    Filed: June 15, 2006
    Date of Patent: November 23, 2010
    Assignees: NEC Corporation, NEC Electronics Corporation
    Inventors: Shintaro Yamamichi, Katsumi Kikuchi, Hideya Murai, Takuo Funaya, Takehiko Maeda, Kenta Ogawa, Jun Tsukano, Hirokazu Honda
  • Publication number: 20100232127
    Abstract: A wiring board composite body includes a supporting substrate, and wiring boards formed on each of the upper and the lower surfaces of the supporting substrate. The supporting substrate includes a supporting body, and a metal body arranged on each of the upper and the lower surfaces of the supporting body. The wiring board comprises at least an insulation layer insulating upper and lower wirings, and a via connecting the upper and the lower wirings. The wiring board mounted on the metal body constitutes a wiring board with the metal body. Thus, the supporting body supporting the metal body is effectively used in a process of forming the wiring board on the metal body, and the wiring board composite body, which has advantageous structural and production characteristics, is provided. A semiconductor device and a method for manufacturing such wiring board composite body and the semiconductor device are also provided.
    Type: Application
    Filed: September 4, 2007
    Publication date: September 16, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Kentaro Mori, Shintaro Yamamichi, Katsumi Kikuchi, Hideya Murai, Takuo Funaya, Takehiko Maeda, Hirokazu Honda, Kenta Ogawa, Jun Tsukano
  • Patent number: 7745736
    Abstract: An interconnecting substrate is provided with a base insulating film having a sunken section in a bottom surface thereof, a first interconnection provided in the sunken section, a via hole formed in the base insulating film, and a second interconnection which is connected to the first interconnection via a conductor within the via hole and is formed on a top surface of the base insulating film, wherein the interconnecting substrate includes a first interconnection pattern formed of the first interconnection which includes at least a linear pattern which extends along a second direction orthogonal to a first direction, and a warpage-controlling pattern which is provided in the sunken section in the bottom surface of the base insulating film and is formed in such a manner as to suppress a warpage of the interconnecting substrate toward a bottom side on both sides of the first direction.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: June 29, 2010
    Assignees: NEC Electronics Corporation, NEC Corporation
    Inventors: Kenta Ogawa, Jun Tsukano, Takehiko Maeda, Tadanori Shimoto, Shintaro Yamamichi, Kazuhiro Baba
  • Publication number: 20100117244
    Abstract: The present invention can avoid spaces not filled with resin by using simplified procedures and configuration even when multiple semiconductor chips are stacked, creating an overhanging portion. A semiconductor device 100 includes a substrate 102; a first semiconductor chip 110 mounted on the substrate 102; a second semiconductor chip 120 stacked over the first semiconductor chip 110, being separated from the first semiconductor chip 110, and provided with a portion overhanging from the first semiconductor chip 110; and an insulating resin 132 which fills a space between the first semiconductor chip 110 and the second semiconductor chip 120 as well as a space between the overhanging portion of the second semiconductor 120 chip and the substrate 102.
    Type: Application
    Filed: November 5, 2009
    Publication date: May 13, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Yuichi Miyagawa, Takehiko Maeda
  • Publication number: 20100105170
    Abstract: A method for manufacturing a semiconductor device includes cutting a resin sealing body into a plurality of pieces. The resin sealing body includes a plurality of semiconductor chips mounted on a wiring board, a heat spreader disposed above the plurality of the semiconductor chips, and sealing resin filled between the wiring board and the heat spreader. The cutting the resin sealing body includes shaving the resin sealing body from a side of the heat spreader and shaving the resin sealing body from a side of the wiring board. The method prevents the heat spreader from generation of burrs.
    Type: Application
    Filed: October 19, 2009
    Publication date: April 29, 2010
    Applicant: NEC Electronics Corporation
    Inventors: Yuko Sato, Takehiko Maeda, Fumiyoshi Kawashiro
  • Patent number: 7701726
    Abstract: A wiring substrate includes a base insulating film, a first interconnection formed on a top surface side of the base insulating film, a via conductor provided in a via hole formed in the base insulating film, and a second interconnection provided on a bottom surface side of the base insulating film, the second interconnection being connected to the first interconnection via the via conductor. The wiring substrate includes divided-substrate-unit regions, in each of which the first interconnection, the via conductor, and the second interconnection are formed.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: April 20, 2010
    Assignees: NEC Electronics Corporation, NEC Corporation
    Inventors: Jun Tsukano, Kenta Ogawa, Takehiko Maeda, Shintaro Yamamichi, Katsumi Kikuchi
  • Patent number: 7674989
    Abstract: A wiring board for mounting a semiconductor element or electronic component having a plurality of wiring layers, an insulating layer provided between these wiring layers, and a via which is provided to the insulating layer and which electrically connects the wiring layers. In this wiring board, the cross-sectional shape of the via in the plane parallel to the wiring layers is obtained by the partial overlapping of a plurality of similar shapes (circles). Stable operation can be obtained in a semiconductor element by minimizing obstacles to increased density, effectively increasing the cross-sectional area of the via, and preventing the wiring resistance from increasing by making the cross-sectional shape of the via into a shape obtained by the partial overlapping of a plurality of similar shapes.
    Type: Grant
    Filed: June 9, 2006
    Date of Patent: March 9, 2010
    Assignees: NEC Electronics Corporation, NEC Corporation
    Inventors: Katsumi Kikuchi, Shintaro Yamamichi, Hideya Murai, Takuo Funaya, Takehiko Maeda, Hirokazu Honda, Kenta Ogawa, Jun Tsukano
  • Patent number: 7649749
    Abstract: A wiring substrate includes a base insulating film, a first interconnection formed on a top surface side of the base insulating film, a via conductor provided in a via formed in the base insulating film, and a second interconnection provided on a bottom surface side of the base insulating film. The second interconnection is connected to the first interconnection via the via. The wiring substrate includes divided-substrate-unit regions, in each of which the first interconnection, the via, and the second interconnection are formed. The wiring substrate includes a warpage-controlling pattern on the base insulating film, with a warped shape such that when the wiring substrate rests on a horizontal plate, at least a central part of a plane surface of the substrate contacts the horizontal plate, with both ends of the side raised.
    Type: Grant
    Filed: July 9, 2007
    Date of Patent: January 19, 2010
    Assignees: NEC Electronics Corporation, NEC Corporation
    Inventors: Jun Tsukano, Kenta Ogawa, Takehiko Maeda, Shintaro Yamamichi, Katsumi Kikuchi
  • Publication number: 20090315190
    Abstract: A wiring board has an insulating layer, a plurality of wiring layers formed in such a way as to be insulated from each other by the insulating layer, and a plurality of vias formed in the insulating layer to connect the wiring layers. Of the wiring layers, a surface wiring layer formed in one surface of the insulating layer include a first metal film exposed from the one surface and a second metal film embedded in the insulating layer and stacked on the first metal film. Edges of the first metal film project from edges of the second metal film in the direction in which the second metal film spreads. By designing the shape of the wiring layers embedded in the insulating layer in this manner, it is possible to obtain a highly reliable wiring board that can be effectively prevented from side etching in the manufacturing process and can adapt to miniaturization and highly dense packaging of wires.
    Type: Application
    Filed: June 29, 2007
    Publication date: December 24, 2009
    Applicant: NEC CORPORATION
    Inventors: Katsumi Kikuchi, Shintaro Yamamichi, Hideya Murai, Takuo Funaya, Kentaro Mori, Takehiko Maeda, Hirokazu Honda, Kenta Ogawa, Jun Tsukano
  • Publication number: 20090294951
    Abstract: A semiconductor device that can be readily manufactured, can include a large number of pads, and can be thin, and a method for manufacturing the same are provided. The semiconductor device is characterized in that the semiconductor device includes an LSI chip, an insulating layer provided on the LSI chip and made of a nonphotosensitive resin, the insulating layer including a via hole in the position corresponding to an externally connected pad, and a wiring layer extending along the insulating layer through the via hole to the externally connected pad, and at least part of the via hole is formed by irradiating the insulating layer with laser light.
    Type: Application
    Filed: January 15, 2008
    Publication date: December 3, 2009
    Applicant: NEC CORPORATION
    Inventors: Hideya Murai, Yuji Kayashima, Takehiko Maeda, Shintaro Yamamichi, Takuo Funaya
  • Publication number: 20090283895
    Abstract: A semiconductor device including a metal frame having a penetrating opening; a semiconductor chip provided in the opening; an insulating layer provided on the upper surface of the metal frame such that the insulating layer covers the upper surface, which is the circuit-formed surface of the semiconductor chip; an interconnect layer provided only on the upper-surface side of the metal frame with intervention of the insulating material and electrically connected to a circuit of the semiconductor chip; a via conductor provided on the upper surface of said semiconductor chip to electrically connect the circuit of the semiconductor chip and the interconnect layer; and a resin layer provided on the lower surface of the metal frame.
    Type: Application
    Filed: October 9, 2007
    Publication date: November 19, 2009
    Applicant: NEC Corporation
    Inventors: Katsumi Kikuchi, Shintaro Yamamichi, Hideya Murai, Katsumi Maeda, Takuo Funaya, Kentaro Mori, Takehiko Maeda, Masaya Kawano, Yuuji Kayashima
  • Publication number: 20090137085
    Abstract: A wiring substrate includes a base insulating film, a first interconnection formed on a top surface side of the base insulating film, a via conductor provided in a via hole formed in the base insulating film, and a second interconnection provided on a bottom surface side of the base insulating film, the second interconnection being connected to the first interconnection via the via conductor. The wiring substrate includes divided-substrate-unit regions, in each of which the first interconnection, the via conductor, and the second interconnection are formed. The wiring substrate includes a warpage-controlling pattern on the base insulating film, and has a warped shape such that when the wiring substrate is left at rest on a horizontal plate, at least a central part of each side of a plane surface of the substrate contacts the horizontal plate, with both ends of the side raised, where each of the sides extends along a second direction perpendicular to a first direction in the plane surface of the substrate.
    Type: Application
    Filed: December 19, 2008
    Publication date: May 28, 2009
    Applicants: NEC ELECTRONICS CORPORATION, NEC CORPORATION
    Inventors: Jun TSUKANO, Kenta Ogawa, Takehiko Maeda, Shintaro Yamamichi, Katsumi Kikuchi
  • Publication number: 20090026636
    Abstract: Semiconductor device has a semiconductor chip embedded in an insulating layer. A semiconductor device comprises a semiconductor chip formed to have external connection pads and a positioning mark that is for via formation; an insulating layer containing a non-photosensitive resin as an ingredient and having a plurality of vias; and wiring electrically connected to the external connection pads through the vias and at least a portion of which is formed on the insulating layer. The insulating layer is formed to have a recess in a portion above the positioning mark. The bottom of the recess is the insulating layer alone. Vias have high positional accuracy relative to the mark.
    Type: Application
    Filed: July 24, 2008
    Publication date: January 29, 2009
    Applicants: NEC CORPORATION, NEC ELECTRONICS CORPORATION
    Inventors: Hideya MURAI, Kentaro Mori, Shintaro Yamamichi, Masaya Kawano, Takehiko Maeda, Kouji Soejima