Abstract: A transparent board is positioned on a support board provided with a positioning mark, and a release material is provided. A semiconductor element is then positioned so that the electrode element faces upward, and the support board is then removed. An insulating resin is then formed on the release material so as to cover the semiconductor element; and a via, a wiring layer, an insulation layer, an external terminal, and a solder resist are then formed. The transparent board is then peeled from the semiconductor device through the use of the release material. A chip can thereby be mounted with high precision, there is no need to provide a positioning mark during mounting of the chip on the substrate in the manufacturing process, and the substrate can easily be removed. As a result, a semiconductor device having high density and a thin profile can be manufactured at low cost.

Abstract: In one embodiment of the present invention, a semiconductor device includes a multilayer wiring board, a DC power supply circuit and a semiconductor integrated circuit chip. The multilayer wiring board has the semiconductor integrated circuit chip embedded therein. The DC power supply circuit is provided on the multilayer wiring board. The DC power supply circuit receives a power supply and converts a voltage of the power supply into a plurality of voltages having different levels from one another. The DC power supply circuit supplies a power supply voltage to the semiconductor integrated circuit chip.

Abstract: A wiring substrate includes a base insulating film, a first interconnection formed on a top surface side of the base insulating film, a via conductor provided in a via hole formed in the base insulating film, and a second interconnection provided on a bottom surface side of the base insulating film, the second interconnection being connected to the first interconnection via the via conductor. The wiring substrate includes divided-substrate-unit regions, in each of which the first interconnection, the via conductor, and the second interconnection are formed. The wiring substrate includes a warpage-controlling pattern on the base insulating film, and has a warped shape such that when the wiring substrate is left at rest on a horizontal plate, at least a central part of each side of a plane surface of the substrate contacts the horizontal plate, with both ends of the side raised, where each of the sides extends along a second direction perpendicular to a first direction in the plane surface of the substrate.

Abstract: A wiring board for mounting a semiconductor element or electronic component having a plurality of wiring layers, an insulating layer provided between these wiring layers, and a via which is provided to the insulating layer and which electrically connects the wiring layers. In this wiring board, the cross-sectional shape of the via in the plane parallel to the wiring layers is obtained by the partial overlapping of a plurality of similar shapes (circles). Stable operation can be obtained in a semiconductor element by minimizing obstacles to increased density, effectively increasing the cross-sectional area of the via, and preventing the wiring resistance from increasing by making the cross-sectional shape of the via into a shape obtained by the partial overlapping of a plurality of similar shapes.

Abstract: A wiring board in which lower-layer wiring composed of a wiring body and an etching barrier layer is formed in a concave portion formed on one face of a board-insulating film, upper-layer wiring is formed on the other face of the board-insulating film, and the upper-layer wiring and the wiring body of the lower-layer wiring are connected to each other through a via hole formed in the board-insulating film. The via hole is barrel-shaped, bell-shaped, or bellows-shaped.

Abstract: An interconnecting substrate is provided with a base insulating film having a sunken section in a bottom surface thereof, a first interconnection provided in the sunken section, a via hole formed in the base insulating film, and a second interconnection which is connected to the first interconnection via a conductor within the via hole and is formed on a top surface of the base insulating film, wherein the interconnecting substrate comprises a first interconnection pattern formed of the first interconnection which comprises at least a linear pattern which extends along a second direction orthogonal to a first direction, and a warpage-controlling pattern which is provided in the sunken section in the bottom surface of the base insulating film and is formed in such a manner as to suppress a warpage of the interconnecting substrate toward a bottom side on both sides of the first direction.

Abstract: A stacked package semiconductor device includes a semiconductor chip package, which has been reduced in thickness through a polishing after being sealed in a resin package, and a semiconductor flip chip electrically connected to the semiconductor chip package through conductive bumps embedded in an underfill resin layer below the semiconductor flip chip; the semiconductor chip package is stacked with the semiconductor flip chip, and the semiconductor flip chip is reduced in thickness through the polishing after the resultant structure is molded in a synthetic resin package; although the semiconductor chip package and semiconductor flip chip are reduced in thickness, the polishing is carried out after the semiconductor chip are sealed in the resin so that the semiconductor chips are less broken during the polishing.

Abstract: A stacked package semiconductor device includes a semiconductor chip package, which has been reduced in thickness through a polishing after being sealed in a resin package, and a semiconductor flip chip electrically connected to the semiconductor chip package through conductive bumps embedded in an underfill resin layer below the semiconductor flip chip; the semiconductor chip package is stacked with the semiconductor flip chip, and the semiconductor flip chip is reduced in thickness through the polishing after the resultant structure is molded in a synthetic resin package; although the semiconductor chip package and semiconductor flip chip are reduced in thickness, the polishing is carried out after the semiconductor chip are sealed in the resin so that the semiconductor chips are less broken during the polishing.

Abstract: A method for fabricating a resin-encapsulated semiconductor device includes the steps of consecutively forming a first interconnect pattern, a dielectric film and a second interconnect pattern on a metallic plate, mounting a semiconductor chip on the dielectric film, connecting chip electrodes of the semiconductor chip to the second interconnect pattern, encapsulating the semiconductor chip on the first dielectric film, removing the metallic plate selectively from the first interconnect pattern, and forming a plurality of metallic bumps on the exposed bottom surface of the first interconnect pattern.

Abstract: Concave portions having shapes adapted to the remaining resist are formed in the vicinities of external terminals of metal wiring. The external terminals of the metal wiring project from the side surfaces of the concave portions. By thus constructing the external terminals, no matter which of the X, Y, and Z directions solder balls that are connected to lands displace in, the lands can displace by following the displacement of the solder balls without restriction. Therefore, even when the semiconductor device and a mounting substrate have elongation differently from each other due to a difference in the coefficient of thermal expansion, the elongation can be absorbed.

Abstract: A method for fabricating a resin-encapsulated semiconductor device includes the steps of consecutively forming a first interconnect pattern, a dielectric film and a second interconnect pattern on a metallic plate, mounting a semiconductor chip on the dielectric film, connecting chip electrodes of the semiconductor chip to the second interconnect pattern, encapsulating the semiconductor chip on the first dielectric film, removing the metallic plate selectively from the first interconnect pattern, and forming a plurality of metallic bumps on the exposed bottom surface of the first interconnect pattern.