Abstract: A current control circuit of a ring oscillator is provided for use in the PLL oscillators.

Abstract: A polarity detector wherein voltage-to-current converters (21, 22) connected to transmission paths (1, 2) output currents according to potentials at the transmission paths (1, 2), respectively, and a current adder (23) adds the currents together. A current-to-voltage converter (24) converts the added current into the voltage (14). And comparators, whose offset voltage is less than 0 V (for example, -5 V) or more than 0 V (for example, 5 V) compare the output voltage (14) with a reference voltage to output signals indicative of whether the output voltage (14) is within a predetermined range, or more than the upper limit of the predetermined range, or less than the lower limit of the predetermined range. The polarity detector for discriminating the polarity of the plurality of transmission paths supplying signals and DC voltages is thus integrated, thereby reducing parts thereof.

Abstract: A differential amplifier (101) includes an input circuit (20), a bias circuit (31) and an output circuit (50). In the input circuit (20), when base potentials of transistors (Q1) and (Q2) change respectively by .DELTA.V and -.DELTA.V thereby changing current flowing through the transistors (Q1) and (Q2) by .DELTA.I and -.DELTA.I, respectively, base-emitter voltages of transistors (Q5) and (Q9) equally increase by .DELTA.V in the bias circuit (31). However, since a base potential of the transistor (Q5) is fixed, an emitter potential of the transistor (Q9) drops by 2.DELTA.V, decreasing a base potential of a transistor (Q4) by 2.DELTA.V. On the other hand, since a current flowing through the transistor (Q4) changes by -.DELTA.I, a base-emitter voltage of the transistor (Q4) accordingly falls by .DELTA.V. This reduces an emitter potential of the transistor (Q4), i.e., a collector potential of the transistor (Q2) by .DELTA.V, and hence, a base-emitter voltage of the transistor (Q2) stays unchanged.

Abstract: An active filter having a frequency characteristics of the fewer variations of manufacturing and the least temperature dependency is provided. A differential amplifier is comprised of resistors 15 and 16 which have a resistance value R.sub.E and are connected in common to a current source 39 in proportion to kT/(qR.sub.0), together with transistors 13 and 14. The transistor 14 is connected to an active load comprised of transistors 18 and 19. The transistor 18 is connected to a current source 31 for producing a current in proportion to a capacity C.sub.0 while the transistor 19 is connected to a current source 30 for producing a current of a remainder of the current produced by the current source 31 subtracted from the current in proportion to 1/R.sub.a. The transistor 19 is further connected to an internal capacitor 21 having capacity C.sub.1. A frequency characteristics of the active filter circuit is determined by the ratio of resistance values R.sub.E, R.sub.0 and R.sub.

Abstract: An integrated circuit (IC 101) has ECL circuits (E3 to En). Bias current (I3) applied to the ECL circuit (E3) is fed by a current mirror circuit consisting of transistors (Q3 and Q1) and resistors (R2 and R3). Constant current (IO) flows in the transistor (Q1) by a constant current circuit (4). The transistor (Q1) has its collector connected to one end of a resistor (R1), the other end of which is connected to a test terminal (2). With an outside resistor (Rb) connected to the test terminal (2) of the integrated circuit (IC 101), part of the constant current (IO) is pulled out to the outside, and the current flowing in the resistor (R2) becomes small. Accordingly, the bias current (I3) is reduced. A voltage difference .DELTA.V of logic states in the ECL circuit (E3) can be controlled from the outside without controlling a temperature, and a test of an inferior transistor the ECL circuit (E3) has can be performed.

Abstract: This invention provides a peak signal detecting device by which a peak of an input signal can be accurately detected even if a noise is caused. A level slice circuit (3) outputs a level slice signal S3 which turns to High/Low depending upon whether an absolute value of a reading signal S0 is more/less than a threshold value VT1. A level slice circuit (5) outputs a level slice signal S5 which turns to High/Low depending upon whether an absolute value of a differentiated signal S1 is more/less than a threshold value VT2. A delay circuit (6) delays a leading edge of the level slice signal S5 for a period T1 and its trailing edge for a period T2 to produce a delay signal S6. At this time, this process is cancelled when the High level of the level slice signal S5 is less than T1. A gate circuit (4) outputs a conjunction of a zero cross signal S2, level slice signal S3 and delay signal S6 as a gate signal S4' (peak detecting signal).

Abstract: Disclosed herein is a magnetic read/write circuit which causes only small fluctuation of an output offset in mode switching. When a head (HD3) is switched to a head (HD6) in read mode, amplifiers (2) and (5) are turned off and on respectively. An offset caused by the amplifier (5) is reduced by negative feedback which is provided by an offset detection circuit (46) and an offset adjusting circuit (5) so that an amplifier (19) will not enhance an offset caused by difference between the amplifiers. During a constant period after mode switching, outputs of an amplifier (40) are transmitted to differential output terminals (26, 27). Input ends of the amplifier (40) are so shorted that an offset of the outputs thereof is suppressed small. After a lapse of the constant period, the outputs of the amplifier (19) are transmitted to the differential output terminals (26, 27).

Abstract: Write transistors Q.sub.1W, Q.sub.2W, Q.sub.3W, Q.sub.4W are arranged in a line, and read transistors Q.sub.1R, Q.sub.2R, Q.sub.3R, Q.sub.4R are also arranged in a line. Wiring pads P11, P12, P13, P14 are arranged between the write and read transistors in a line parallel to both of the lines. Heat generated by a write operation in the write transistors does not significantly influence the read transistors in a read operation. The influences are exerted on the read transistors approximately uniformly, so that an offset voltage difference can be minimized in differential amplification.

Abstract: A semiconductor integrated circuit (1) is provided therein with a current mirror circuit comprising a first transistor (Q4) through which a reference current flows from a current source (15) connected with one electrode of the first transistor (Q1) and a second transistor (Q5) which supplies a current responsive to the ratio of first and second external resistors (20, 21) connected with other electrodes of the first and second transistors (Q4, Q5) on the basis of the reference current. The current from the second transistor (Q5) flows through an internal resistor (16) connected with one electrode of the second transistor (Q5), so that a threshold voltage is generated across the internal resistor (16). The threshold voltage can be arbitrarily set in accordance with the ratio of the first and second external resistors (20, 21).

Abstract: In a sampling mode, a servo signal sampling and holding switch (4.sub.a) and a reference voltage sampling and holding switch (30.sub.a) are turned off, so that transistors (Q.sub.7a, Q.sub.5a) are turned on. In response to on states of the transistors (Q.sub.7a, Q.sub.5a), capacities (C.sub.3a, C.sub.30a) are charged with the peak voltage (V.sub.ref +(1/2)V.sub.s) of a servo signal and a reference voltage (V.sub.ref), respectively. In a holding mode, the sampling and holding switches (4.sub.a, 30.sub.a) are turned on, so that the transistors (Q.sub.7a, Q.sub.5a) are turned off. the charging voltages (D, E) of the capacitors (C.sub.3a, C.sub.30a) are discharged through post-stage buffers (5.sub.a, 3.sub.a), so that they include offsets which are canceled through a subtractor (6.sub.a).