Patents by Inventor Takeo Furuhata
Takeo Furuhata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7679127Abstract: A semiconductor device including a semiconductor substrate; a first gate insulating film formed on the semiconductor substrate; a first gate electrode layer formed on the first gate insulating film; an element isolation insulating film formed so as to isolate a plurality of the first gate electrode layers; a second gate insulating film layer formed so as to cover upper surfaces of the plurality of first gate electrode layers and the element isolation insulating films; and a second gate electrode layer formed on the second gate insulating film layer; and the second gate insulating film layer includes a NONON stacked film structure and a nitride film layer contacting the first gate electrode layer and constituting a lowermost layer of the NONON stack film structure is separated at a portion interposing the plurality of neighboring first gate electrode layers.Type: GrantFiled: June 27, 2007Date of Patent: March 16, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Junichi Shiozawa, Takeo Furuhata, Akiko Sekihara
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Patent number: 7598562Abstract: A semiconductor device including a semiconductor substrate; an element isolation region having a trench filled with an insulating film defined on the semiconductor substrate; a memory cell transistor formed in an element forming region isolated by the element isolating regions of the semiconductor substrate; and the memory cell transistor includes a gate insulating film formed on a surface of the element forming region; a floating gate formed over the gate insulating film; an inter-gate insulating film formed integrally so as to cover the floating gate and the insulating film of the element isolation region and having high dielectric constant in a portion corresponding to the floating gate and low dielectric constant in a portion corresponding to the insulating film of the element isolation region; and a control gate stacked over the floating gate via the inter-gate insulating film.Type: GrantFiled: June 27, 2007Date of Patent: October 6, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Hajime Nagano, Takeo Furuhata
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Publication number: 20090152618Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate, a first insulation layer formed on the semiconductor substrate, a charge storage layer formed on the first insulation layer, a second insulation layer formed on the charge storage layer, a control electrode formed on the second insulation layer. The second insulation layer includes a first silicon oxide film, an intermediate insulating film formed on the first silicon oxide film and having a relative permittivity of not less than 7, and a second silicon oxide film formed on the intermediate insulating film. A charge trap layer is formed at least in either first or second silicon oxide film or a boundary between the first silicon oxide film and the intermediate insulating film or a boundary between the second silicon oxide film and the intermediate insulating film.Type: ApplicationFiled: December 12, 2008Publication date: June 18, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazuhiro Matsuo, Masayuki Tanaka, Takeo Furuhata, Koji Nakahara
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Publication number: 20080121972Abstract: A semiconductor device including a semiconductor substrate; a first gate insulating film formed on the semiconductor substrate; a first gate electrode layer formed on the first gate insulating film; an element isolation insulating film formed so as to isolate a plurality of the first gate electrode layers; a second gate insulating film layer formed so as to cover upper surfaces of the plurality of first gate electrode layers and the element isolation insulating films; and a second gate electrode layer formed on the second gate insulating film layer; and the second gate insulating film layer includes a NONON stacked film structure and a nitride film layer contacting the first gate electrode layer and constituting a lowermost layer of the NONON stack film structure is separated at a portion interposing the plurality of neighboring first gate electrode layers.Type: ApplicationFiled: June 27, 2007Publication date: May 29, 2008Applicant: Kabushiki Kaisha ToshibaInventors: Junichi Shiozawa, Takeo Furuhata, Akiko Sekihara
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Publication number: 20080014697Abstract: A semiconductor device including a semiconductor substrate a trench forming in the substrate, an insulating film forming on an inner surface of the trench so as to be rendered thicker from a substrate surface side thereof toward a trench deep side thereof, and an electrode layer forming inside the insulating film forming inside the trench so as to extend from a trench deep part side toward the surface side of the substrate. The substrate surface side of the insulating film functions as a collar insulating film retaining an insulation performance between the electrode layer and the semiconductor substrate, and the trench deep side of the insulating film functions as a capacitor insulating film composing a capacitor of a DRAM cell.Type: ApplicationFiled: July 16, 2007Publication date: January 17, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takeo FURUHATA, Takahito Nakajima
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Publication number: 20070296016Abstract: A semiconductor device including a semiconductor substrate; an element isolation region having a trench filled with an insulating film defined or the semiconductor substrate; a memory cell transistor formed in an element forming region isolated by the element isolating regions of the semiconductor substrate; and the memory cell transistor includes a gate insulating film formed on a surface of the element forming region; a floating gate formed over the gate insulating film; an inter-gate insulating film formed integrally so as to cover the floating gate and the insulating film of the element isolation region and having high dielectric constant in a portion corresponding to the floating gate and low dielectric constant in a portion corresponding to the insulating film of the element isolation region; and a control gate stacked over the floating gate via the inter-gate insulating film.Type: ApplicationFiled: June 27, 2007Publication date: December 27, 2007Applicant: Kabushiki Kaisha ToshibaInventors: Hajime Nagano, Takeo Furuhata
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Patent number: 7265020Abstract: A method of manufacturing a semiconductor device includes forming a trench in a semiconductor substrate, isotropically forming a trench surface insulating film on an inner surface of the trench, the trench surface insulating film including a deep part functioning as a capacitor insulating film, forming a surface layer side insulating film on the inner surface of the trench so that the surface layer side insulating film is continuously rendered thinner from the surface side of the substrate toward the deep side of the trench, and forming an electrode layer inside the surface layer side insulating film and the trench surface insulating film both formed on the inner surface of the trench.Type: GrantFiled: September 27, 2005Date of Patent: September 4, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Takeo Furuhata, Takahito Nakajima
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Patent number: 7126178Abstract: A semiconductor device comprises a semiconductor substrate; a trench formed in the semiconductor substrate or in a layer deposited on the semiconductor substrate; a first conductive layer deposited in the trench and having a recess in the top surface thereof; a buried layer which buries the recess of the first conductive layer and which is made of a material having a melting point lower than that of the first conductive layer; and a second conductive layer formed on the buried layer inside the trench and electrically connected to the first conductive layer.Type: GrantFiled: March 2, 2005Date of Patent: October 24, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Takeo Furuhata, Ichiro Mizushima, Akiko Sekihara, Motoya Kishida, Tsubasa Harada, Takashi Nakao
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Patent number: 7065469Abstract: A manufacturing apparatus which includes a rotary machine, includes: a plurality of accelerometers configured to measure diagnosis time series data attached to the rotary machine at locations where variations of the rotary machine are different; a frequency analysis device configured to perform a frequency analysis on the diagnosis time series data measured by the plurality of accelerometers; a time series data recording module configured to generate diagnosis data based on variations in characteristics of vibration corresponding to an analysis target frequency and to record the diagnosis data; and a life prediction unit configured to analyze the diagnosis data to determine a life span of the rotary machine.Type: GrantFiled: March 19, 2003Date of Patent: June 20, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Shuichi Samata, Takeo Furuhata, Yukihiro Ushiku, Akihito Yamamoto, Takashi Nakao
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Publication number: 20060097303Abstract: A semiconductor device comprises a semiconductor substrate; a trench formed in the semiconductor substrate or in a layer deposited on the semiconductor substrate; a first conductive layer deposited in the trench and having a recess in the top surface thereof; a buried layer which buries the recess of the first conductive layer and which is made of a material having a melting point lower than that of the first conductive layer; and a second conductive layer formed on the buried layer inside the trench and electrically connected to the first conductive layer.Type: ApplicationFiled: December 21, 2005Publication date: May 11, 2006Inventors: Takeo Furuhata, Ichiro Mizushima, Akiko Sekihara, Motoya Kishida, Tsubasa Harada, Takashi Nakao
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Publication number: 20060068544Abstract: A method of manufacturing a semiconductor device includes forming a trench in a semiconductor substrate, isotropically forming a trench surface insulating film on an inner surface of the trench, the trench surface insulating film including a deep part functioning as a capacitor insulating film, forming a surface layer side insulating film on the inner surface of the trench so that the surface layer side insulating film is continuously rendered thinner from the surface side of the substrate toward the deep side of the trench, and forming an electrode layer inside the surface layer side insulating film and the trench surface insulating film both formed on the inner surface of the trench.Type: ApplicationFiled: September 27, 2005Publication date: March 30, 2006Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takeo Furuhata, Takahito Nakajima
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Patent number: 6982198Abstract: A semiconductor device comprises a semiconductor substrate; a trench formed in the semiconductor substrate or in a layer deposited on the semiconductor substrate; a first conductive layer deposited in the trench and having a recess in the top surface thereof; a buried layer which buries the recess of the first conductive layer and which is made of a material having a melting point lower than that of the first conductive layer; and a second conductive layer formed on the buried layer inside the trench and electrically connected to the first conductive layer.Type: GrantFiled: March 2, 2005Date of Patent: January 3, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Takeo Furuhata, Ichiro Mizushima, Akiko Sekihara, Motoya Kishida, Tsubasa Harada, Takashi Nakao
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Patent number: 6946699Abstract: A semiconductor device comprises a semiconductor substrate; a trench formed in the semiconductor substrate or in a layer deposited on the semiconductor substrate; a first conductive layer deposited in the trench and having a recess in the top surface thereof; a buried layer which buries the recess of the first conductive layer and which is made of a material having a melting point lower than that of the first conductive layer; and a second conductive layer formed on the buried layer inside the trench and electrically connected to the first conductive layer.Type: GrantFiled: April 10, 2003Date of Patent: September 20, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Takeo Furuhata, Ichiro Mizushima, Akiko Sekihara, Motoya Kishida, Tsubasa Harada, Takashi Nakao
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Publication number: 20050170582Abstract: A semiconductor device comprises a semiconductor substrate; a trench formed in the semiconductor substrate or in a layer deposited on the semiconductor substrate; a first conductive layer deposited in the trench and having a recess in the top surface thereof; a buried layer which buries the recess of the first conductive layer and which is made of a material having a melting point lower than that of the first conductive layer; and a second conductive layer formed on the buried layer inside the trench and electrically connected to the first conductive layer.Type: ApplicationFiled: March 2, 2005Publication date: August 4, 2005Applicant: Kabushiki Kaisha ToshibaInventors: Takeo Furuhata, Ichiro Mizushima, Akiko Sekihara, Motoya Kishida, Tsubasa Harada, Takashi Nakao
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Publication number: 20050167720Abstract: A semiconductor device comprises a semiconductor substrate; a trench formed in the semiconductor substrate or in a layer deposited on the semiconductor substrate; a first conductive layer deposited in the trench and having a recess in the top surface thereof; a buried layer which buries the recess of the first conductive layer and which is made of a material having a melting point lower than that of the first conductive layer; and a second conductive layer formed on the buried layer inside the trench and electrically connected to the first conductive layer.Type: ApplicationFiled: March 2, 2005Publication date: August 4, 2005Applicant: Kabushiki Kaisha ToshibaInventors: Takeo Furuhata, Ichiro Mizushima, Akiko Sekihara, Motoya Kishida, Tsubasa Harada, Takashi Nakao
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Patent number: 6898551Abstract: A system for predicting life of a rotary machine, includes a vibration gauge configured to measure time series data of a peak acceleration of the rotary machine; a band pass filter configured to filter an analog signal of the time series data of the peak acceleration measured by the vibration gauge in a frequency band including a first analysis frequency expressed as a product of an equation including a number of rotor blades of the rotary machine and a normal frequency unique to the rotary machine; and a data processing unit configured to predict a life span of the rotary machine by characteristics of the filtered analog data of the time series data of the peak acceleration with the first analysis frequency.Type: GrantFiled: April 18, 2003Date of Patent: May 24, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Shuichi Samata, Yukihiro Ushiku, Akihito Yamamoto, Takashi Nakao, Takeo Furuhata
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Publication number: 20050107984Abstract: A method for predicting life of a rotary machine used in a manufacturing apparatus, includes: determining a starting time of an abnormal condition just before a failure of a monitor rotary machine used in a monitor manufacturing process, from monitor time-series data for characteristics of the monitor rotary machine, statistically analyzing the monitor time-series data, and finding a value for the characteristics at the starting time of the abnormal condition as a threshold of the abnormal condition; measuring diagnosis time-series data for the characteristic of a motor current of a diagnosis rotary machine during a manufacturing process; preparing diagnosis data from the diagnosis time-series data; and determining a time for the diagnosis data exceeding the threshold as the life of the diagnosis rotary machine.Type: ApplicationFiled: December 27, 2004Publication date: May 19, 2005Inventors: Shuichi Samata, Yukihiro Ushiku, Takashi Nakao, Takeo Furuhata
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Patent number: 6885972Abstract: A method for predicting life span of a rotary machine used in a manufacturing apparatus, includes: measuring rotary machine acceleration evaluation time series data with a sampling interval being less than a half the cycle of an analysis target frequency, a number of samplings being at least four times the analysis target frequency; generating evaluation diagnosis data based on variations in characteristics corresponding to the analysis target frequency by subjecting the evaluation time series data to frequency analysis; and determining the life span of the rotary machine using the evaluation diagnosis data.Type: GrantFiled: August 28, 2002Date of Patent: April 26, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Shuichi Samata, Yukihiro Ushiku, Takeo Furuhata, Takashi Nakao, Ken Ishii
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Patent number: 6794713Abstract: SiGe or SiC films are selectively grown on source/drain regions, followed by selectively growing silicon. A monocrystalline film having a high dislocation density or a polycrystalline film can be grown in growing the silicon film by making the C or Ge concentration higher than a predetermined level. The silicon layer on each of the source/drain regions is not monocrystalline or, even if monocrystalline, has a high density of dislocation. Therefore, the silicon film formed thereon is in the form of a monocrystalline silicon film having a high dislocation density or a polycrystalline silicon film. It is possible to suppress an impurity diffusion to reach a deep region caused by channeling of ions generated in the doping step by means of an ion implantation.Type: GrantFiled: September 5, 2003Date of Patent: September 21, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Ichiro Mizushima, Shigehiko Saida, Takeo Furuhata, Yoshitaka Tsunashima
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Publication number: 20040106254Abstract: A semiconductor device comprises a semiconductor substrate; a trench formed in the semiconductor substrate or in a layer deposited on the semiconductor substrate; a first conductive layer deposited in the trench and having a recess in the top surface thereof; a buried layer which buries the recess of the first conductive layer and which is made of a material having a melting point lower than that of the first conductive layer; and a second conductive layer formed on the buried layer inside the trench and electrically connected to the first conductive layer.Type: ApplicationFiled: April 10, 2003Publication date: June 3, 2004Inventors: Takeo Furuhata, Ichiro Mizushima, Akiko Sekihara, Motoya Kishida, Tsubasa Harada, Takashi Nakao