Abstract: A synapse memory system includes a plurality of synapse memory cells, a write portion, and read drivers. Each synapse memory cells is disposed at cross points of axon lines and dendrite lines and includes a plurality of analog memory devices and each synapse memory cell is configured to store a weight value according to an output level of a write signal. The plurality of analog memory devices is combined to constitute each synapse memory cell. The write portion is configured to write the weight value to each synapse memory cell and includes a write driver and an output controller. The write driver is configured to output the write signal to each synapse memory cell and the output controller is configured to control the output level of the write signal of the write driver. The read drivers are configured to read the weight value stored in the synapse memory cells.

Abstract: A synapse memory system includes a plurality of synapse memory cells, a write portion, and read drivers. Each synapse memory cells is disposed at cross points of axon lines and dendrite lines and includes a plurality of analog memory devices and each synapse memory cell is configured to store a weight value according to an output level of a write signal. The plurality of analog memory devices is combined to constitute each synapse memory cell. The write portion is configured to write the weight value to each synapse memory cell and includes a write driver and an output controller. The write driver is configured to output the write signal to each synapse memory cell and the output controller is configured to control the output level of the write signal of the write driver. The read drivers are configured to read the weight value stored in the synapse memory cells.

Abstract: A superconducting multi-stage synchronous logic circuit structure includes a first clocked logic gate, a second clocked logic gate, and an unclocked logic gate. Each of the logic gates includes Josephson junctions. The first clocked logic gate has a single first clocked logic gate output; the second clocked logic gate has a single second clocked logic gate output. The unclocked logic gate has a first input connected in electrical communication with the first clocked logic gate output and has a second input connected in electrical communication with the second clocked logic gate output, and has a single output. The Josephson junctions of the unclocked logic gate are arranged such that, in a single clock cycle that drives the first clocked logic gate and the second clocked logic gate, the unclocked logic gate produces a single signal in response to the inputs of the first and second clocked logic gates.

Abstract: Systems and methods for optimizing a pipeline are described. A system can generate at least one pair of single flux quantum (SFQ) clock signals based on a stream of SFQ pulses. Each pair of SFQ clock signals can include a first SFQ clock signal and a second SFQ clock signal that is out of phase with the first SFQ clock signal. The second SFQ clock signal can have the same frequency as the first SFQ clock signal. The system can define, for each pair of SFQ clock signals, a first clock cycle and a second clock cycle based on the first SFQ clock signal and the second SFQ clock signal. The second clock cycle can be greater than the first clock cycle. The system can assign the first and second clock cycles to different stages of a pipeline based on delays by the different stages.

Abstract: A computer-implemented method for processing signals is provided including advantageously generating a temporally continuous weighted pulse position modulation (CW PPM) duration signal from an input analog signal, converting the CW PPM duration signal to a memory access signal, executing a multiply and accumulate (MAC) operation with the memory access signal, and advantageously generating the input analog signal from a result of the MAC operation by an activation function (AF).

Abstract: A neuromorphic synapse array includes a plurality of synaptic array cells being connected by circuitry such that the synaptic array cells are assigned to rows and columns of an array, the synaptic array cells respectively having a single polarity synapse weight, the rows respectively connected to respective input ends of the synaptic array cells, the columns respectively connected to respective output ends of the synaptic array cells, the synaptic array cells aligned in a column of the array being defined as operation column arrays and an array of current mirrors, each current mirror exhibiting a mirror ratio of N:1, wherein N is a number of columns of the synaptic array cells, respectively connected to the respective rows such that weights corresponding to all of the current mirrors are set to average weights of all of the synaptic array cells that are updated during a learning phase.

Abstract: A neuromorphic synapse array includes a plurality of synaptic array cells being connected by circuitry such that the synaptic array cells are assigned to rows and columns of an array, the synaptic array cells respectively having a single polarity synapse weight, the rows respectively connected to respective input ends of the synaptic array cells, the columns respectively connected to respective output ends of the synaptic array cells, the synaptic array cells aligned in a column of the array being defined as operation column arrays and an array of current mirrors, each current mirror exhibiting a mirror ratio of N:1, wherein N is a number of columns of the synaptic array cells, respectively connected to the respective rows such that weights corresponding to all of the current mirrors are set to average weights of all of the synaptic array cells that are updated during a learning phase.

Abstract: A synapse memory and a method for reading a weight value stored in a synapse memory are provided. The synapse memory includes a memory device configured to store a weight value. The memory device includes a read terminal, a write terminal, and a common terminal, the read terminal being configured to receive a read signal, the write terminal being configured to receive a write signal, and the common terminal being configured to output an output signal from the memory device. The synapse memory also includes a write transistor provided between the write terminal of the memory device and a write signal line configured to send the write signal. The synapse memory further includes a common transistor provided between the common terminal of the memory device and one of the dendrite lines.

Abstract: A synapse memory and a method for reading a weight value stored in a synapse memory are provided. The synapse memory includes a memory device configured to store a weight value. The memory device includes a read terminal, a write terminal, and a common terminal, the read terminal being configured to receive a read signal, the write terminal being configured to receive a write signal, and the common terminal being configured to output an output signal from the memory device. The synapse memory also includes a write transistor provided between the write terminal of the memory device and a write signal line configured to send the write signal. The synapse memory further includes a common transistor provided between the common terminal of the memory device and one of the dendrite lines.

Abstract: A computer-implemented method for processing signals is provided including advantageously generating a temporally continuous weighted pulse position modulation (CW PPM) duration signal from an input analog signal, converting the CW PPM duration signal to a memory access signal, executing a multiply and accumulate (MAC) operation with the memory access signal, and advantageously generating the input analog signal from a result of the MAC operation by an activation function (AF).

Abstract: A synapse memory system includes synapse memory cells, each of which includes a non-volatile random access memory (NVRAM). Each synapse memory cell is configured to store a weight value according to an output level of a write signal. A write portion is configured to write the weight value to each synapse memory cell and includes a write driver and an output controller. The write driver is configured to output the write signal to each synapse memory cell. The output controller is configured to control the output level of the write signal of the write driver. Read drivers are configured to read the weight value stored in the synapse memory cells. The output controller is configured to control the output level of the write signal in updating the weight value in the synapse memory cell, to compensate for weight value variation according to a device characteristic of the NVRAM.

Abstract: A neuromorphic synapse array includes a plurality of synaptic array cells being connected by circuitry such that the synaptic array cells are assigned to rows and columns of an array, the synaptic array cells respectively having a single polarity synapse weight, the rows respectively connected to respective input ends of the synaptic array cells, the columns respectively connected to respective output ends of the synaptic array cells, the synaptic array cells aligned in a column of the array being defined as operation column arrays and an array of current mirrors, each current mirror exhibiting a mirror ratio of N:1, wherein N is a number of columns of the synaptic array cells, respectively connected to the respective rows such that weights corresponding to all of the current mirrors are set to average weights of all of the synaptic array cells that are updated during a learning phase.

Abstract: A synapse memory system includes: synapse memory cells provided at cross points of axon lines and dendrite lines, each synapse memory cell being associated with nonvolatile random-access memory (NVRAM), each synapse memory cell being configured to store a weight value according to an output level of a write signal; a write portion configured to write the weight value to each synapse memory cell, the write portion including a write driver and an output controller, the write driver being a digital driver configured to output the write signal to a subject synapse memory cell, the output controller being configured to control the output level of the write signal of the write driver; and read drivers configured to read the weight value stored in the synapse memory cells.

Abstract: Embodiments include methods and systems of neuron leaky integrate and fire circuit (NLIFC). Aspects include: receiving an input current having both AC component and DC component at an input terminal of the NLIFC, extracting AC component of input current, generating a number of swing voltages at a swing node using extracted AC component of the input current, transferring charge from a pull-up node to a neuron membrane potential (NP) node through an integration diode and a pull-up diode to raise a voltage at NP node over an integration capacitor gradually and the voltage at NP node shows integration value of AC component of input current, implementing leaky decay function of the neuron leaky integrate and fire circuit, detecting a timing of neuron fire using an analog comparator, resetting a neuron membrane potential level for a refractory period after neuron fire, and generating fire output signal of the NLIFC.

Abstract: A neuromorphic synapse array is provided which ensures that a neuron model as such McCulloch-Pitts is dependent on nonlinearity with a single polarity weight cell. The neuromorphic synapse array includes a plurality of synaptic array cells, a plurality of operation column arrays, and a reference column array. The synaptic array cells respectively have a single polarity synapse weight and are classified into operation synapse cells and reference synapse cells for shifting a product-sum of the operation synapse cells. The operation column arrays are defined by the operation synapse cells aligned in column of the array. The reference column array is defined by the reference synapse cells aligned in column of the array.

Abstract: An analog Magnetoresistive Random Access Memory (MRAM) cell is provided. The analog MRAM cell includes a magnetic free layer having a first domain having a first magnetization direction, a second domain having a second magnetization direction opposite to the first magnetization direction and a domain wall located between the first domain and the second domain. The analog MRAM cell further includes a magnetically pinned layer. The analog MRAM cell also includes an insulating tunnel barrier between the magnetic free layer and the magnetically pinned layer. The analog MRAM cell additionally includes an electrode located adjacent to the magnetic free layer configured to generate heat by supplying current to decrease a conductance of the magnetic free layer.

Abstract: A synapse memory system includes a plurality of synapse memory cells, a write portion, and read drivers. Each synapse memory cells is disposed at cross points of axon lines and dendrite lines and includes a plurality of analog memory devices and each synapse memory cell is configured to store a weight value according to an output level of a write signal. The plurality of analog memory devices is combined to constitute each synapse memory cell. The write portion is configured to write the weight value to each synapse memory cell and includes a write driver and an output controller. The write driver is configured to output the write signal to each synapse memory cell and the output controller is configured to control the output level of the write signal of the write driver. The read drivers are configured to read the weight value stored in the synapse memory cells.

Abstract: A synapse memory system includes synapse memory cells, each of which includes a non-volatile random access memory (NVRAM). Each synapse memory cell is configured to store a weight value according to an output level of a write signal. A write portion is configured to write the weight value to each synapse memory cell and includes a write driver and an output controller. The write driver is configured to output the write signal to each synapse memory cell. The output controller is configured to control the output level of the write signal of the write driver. Read drivers are configured to read the weight value stored in the synapse memory cells. The output controller is configured to control the output level of the write signal in updating the weight value in the synapse memory cell, to compensate for weight value variation according to a device characteristic of the NVRAM.

Abstract: Methods and systems are provided for operating a neuromorphic system for generating neuron and synapse activities. The method includes: preparing at least one digital timer in the neuromorphic system, each of the at least one digital timers including multi-bit digital values; generating time signals using the at least one digital timer; emulating an analog waveform of a neuron spike; updating parameters of the neuromorphic system using the time signals and the current values of the parameters; presetting, using a processor, the digital values of the at least one digital timer to initial values when the spike input is provided to the node; and updating, using the processor, the digital values of the at least one digital timer with a specified amount when there is an absence of a spike input to the node.

Abstract: A method and system are provided for updating synapse weight values in neuromorphic system with Spike Time Dependent Plasticity model. The method includes selectively performing, by a hardware-based synapse weight incrementer or decrementer, one of a synapse weight increment function or decrement function, each using a respective lookup table, to generate updated synapse weight values responsive to spike timing data. The method further includes storing the updated synapse weight values in a memory. The method additionally includes performing, by a hardware-based processor, a learning process to integrate the updated synapse weight values stored in the memory into the Spike Time Dependent Plasticity model neuromorphic system for improved neuromorphic simulation.