Patents by Inventor Takeo Yasuda

Takeo Yasuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10643125
    Abstract: Embodiments include methods and systems of neuron leaky integrate and fire circuit (NLIFC). Aspects include: receiving an input current having both AC component and DC component at an input terminal of the NLIFC, extracting AC component of input current, generating a number of swing voltages at a swing node using extracted AC component of the input current, transferring charge from a pull-up node to a neuron membrane potential (NP) node through an integration diode and a pull-up diode to raise a voltage at NP node over an integration capacitor gradually and the voltage at NP node shows integration value of AC component of input current, implementing leaky decay function of the neuron leaky integrate and fire circuit, detecting a timing of neuron fire using an analog comparator, resetting a neuron membrane potential level for a refractory period after neuron fire, and generating fire output signal of the NLIFC.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: May 5, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark B. Ritter, Takeo Yasuda
  • Patent number: 10552731
    Abstract: Described is a neuromorphic system implemented in hardware that implements neuron membrane potential update based on the leaky integrate and fire (LIF) model. The system further models synapse weights update based on the spike time-dependent plasticity (STDP) model. The system includes an artificial neural network in which the update scheme of neuron membrane potential and synapse weight are effectively defined and implemented.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: February 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Takeo Yasuda, Kohji Hosokawa, Yutaka Nakamura, Junka Okazawa, Masatoshi Ishii
  • Publication number: 20200026994
    Abstract: Embodiments include methods and systems of neuron leaky integrate and fire circuit (NLIFC). Aspects include: receiving an input current having both AC component and DC component at an input terminal of the NLIFC, extracting AC component of input current, generating a number of swing voltages at a swing node using extracted AC component of the input current, transferring charge from a pull-up node to a neuron membrane potential (NP) node through an integration diode and a pull-up diode to raise a voltage at NP node over an integration capacitor gradually and the voltage at NP node shows integration value of AC component of input current, implementing leaky decay function of the neuron leaky integrate and fire circuit, detecting a timing of neuron fire using an analog comparator, resetting a neuron membrane potential level for a refractory period after neuron fire, and generating fire output signal of the NLIFC.
    Type: Application
    Filed: September 26, 2019
    Publication date: January 23, 2020
    Inventors: Mark B. Ritter, Takeo Yasuda
  • Publication number: 20190354845
    Abstract: Described is a neuromorphic system implemented in hardware that implements neuron membrane potential update based on the leaky integrate and fire (LIF) model. The system further models synapse weights update based on the spike time-dependent plasticity (STDP) model. The system includes an artificial neural network in which the update scheme of neuron membrane potential and synapse weight are effectively defined and implemented.
    Type: Application
    Filed: July 30, 2019
    Publication date: November 21, 2019
    Inventors: Takeo Yasuda, Kohji Hosokawa, Yutaka Nakamura, Junka Okazawa, Masatoshi Ishii
  • Patent number: 10446231
    Abstract: A memory cell structure includes a plurality of write lines arranged for writing a synapse state to a synapse memory cell including a plurality of cell components each including at least one unit cell, each of the plurality of write lines being used for writing the synapse state by writing a first set of states to a corresponding cell component of the plurality of cell components by writing one of a second set of states to each unit cell included in the corresponding cell component, and the first set depending on the second set.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: October 15, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kohji Hosokawa, Masatoshi Ishii, Takeo Yasuda
  • Publication number: 20190228292
    Abstract: A synapse memory and a method for reading a weight value stored in a synapse memory are provided. The synapse memory includes a memory device configured to store a weight value. The memory device includes a read terminal, a write terminal, and a common terminal, the read terminal being configured to receive a read signal, the write terminal being configured to receive a write signal, and the common terminal being configured to output an output signal from the memory device. The synapse memory also includes a write transistor provided between the write terminal of the memory device and a write signal line configured to send the write signal. The synapse memory further includes a common transistor provided between the common terminal of the memory device and one of the dendrite lines.
    Type: Application
    Filed: January 24, 2018
    Publication date: July 25, 2019
    Inventors: Takeo Yasuda, Kohji Hosokawa
  • Publication number: 20190228295
    Abstract: A synapse memory system includes: synapse memory cells provided at cross points of axon lines and dendrite lines, each synapse memory cell being associated with nonvolatile random-access memory (NVRAM), each synapse memory cell being configured to store a weight value according to an output level of a write signal; a write portion configured to write the weight value to each synapse memory cell, the write portion including a write driver and an output controller, the write driver being a digital driver configured to output the write signal to a subject synapse memory cell, the output controller being configured to control the output level of the write signal of the write driver; and read drivers configured to read the weight value stored in the synapse memory cells.
    Type: Application
    Filed: January 19, 2018
    Publication date: July 25, 2019
    Inventors: Takeo Yasuda, Masatoshi Ishii
  • Publication number: 20190206490
    Abstract: A memory cell structure includes a plurality of write lines arranged for writing a synapse state to a synapse memory cell including a plurality of cell components each including at least one unit cell, each of the plurality of write lines being used for writing the synapse state by writing a first set of states to a corresponding cell component of the plurality of cell components by writing one of a second set of states to each unit cell included in the corresponding cell component, and the first set depending on the second set.
    Type: Application
    Filed: March 6, 2019
    Publication date: July 4, 2019
    Inventors: Kohji Hosokawa, Masatoshi Ishii, Takeo Yasuda
  • Patent number: 10297321
    Abstract: A memory cell structure includes a plurality of write lines arranged for writing a synapse state to a synapse memory cell including a plurality of cell components each including at least one unit cell, each of the plurality of write lines being used for writing the synapse state by writing a first set of states to a corresponding cell component of the plurality of cell components by writing one of a second set of states to each unit cell included in the corresponding cell component, the first and second sets each having a predetermined number of states, and the first set depending on the second set, and a read line arranged for reading the synapse state from the synapse memory cell.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: May 21, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kohji Hosokawa, Masatoshi Ishii, Takeo Yasuda
  • Publication number: 20180322920
    Abstract: A memory cell structure includes a plurality of write lines arranged for writing a synapse state to a synapse memory cell including a plurality of cell components each including at least one unit cell, each of the plurality of write lines being used for writing the synapse state by writing a first set of states to a corresponding cell component of the plurality of cell components by writing one of a second set of states to each unit cell included in the corresponding cell component, the first and second sets each having a predetermined number of states, and the first set depending on the second set, and a read line arranged for reading the synapse state from the synapse memory cell.
    Type: Application
    Filed: July 11, 2018
    Publication date: November 8, 2018
    Inventors: Kohji Hosokawa, Masatoshi Ishii, Takeo Yasuda
  • Patent number: 10090047
    Abstract: A memory cell structure includes a synapse memory cell including plural cell components, each of the plural cell components including a unit cell, plural write lines arranged for writing a synapse state to the synapse memory cell, each of the plural write lines being used for writing one of a first set of a predetermined number of states to a corresponding cell component by writing one of a second set of the predetermined number of states to the unit cell included in the corresponding cell component, the first set depending on the second set and a number of the unit cell included in the corresponding cell component, and a read line arranged for reading the synapse state from the synapse memory cell, the read line being used for reading one of the first set of the predetermined number of states from all of the plural cell components simultaneously.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: October 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kohji Hosokawa, Masatoshi Ishii, Takeo Yasuda
  • Patent number: 9996317
    Abstract: A barrel shifter uses a sign magnitude to 2's complement converter to generate decoder signals for its cascaded multiplexer selectors. The sign input receives the shift direction and the magnitude input receives the shift amount. The sign magnitude to 2's complement converter computes an output result as a 2's complement of the shift amount using the shift direction as a sign input, assigns a first portion (most significant bit half) of the output result to a first decoder signal, and assigns a second portion (least significant bit half) of the output result to a second decoder signal. This encoding scheme allows the decoder circuits to be relatively simple, for example, 3-to-8 decoders for an implementation adapted to shift a 64-bit operand value rather than the 4-to-9 decoder required in a conventional barrel shifter, leading to faster operation, less area, and reduced power consumption.
    Type: Grant
    Filed: January 31, 2015
    Date of Patent: June 12, 2018
    Assignee: International Business Machines Corporation
    Inventor: Takeo Yasuda
  • Publication number: 20180130528
    Abstract: A memory cell structure includes a synapse memory cell including plural cell components, each of the plural cell components including a unit cell, plural write lines arranged for writing a synapse state to the synapse memory cell, each of the plural write lines being used for writing one of a first set of a predetermined number of states to a corresponding cell component by writing one of a second set of the predetermined number of states to the unit cell included in the corresponding cell component, the first set depending on the second set and a number of the unit cell included in the corresponding cell component, and a read line arranged for reading the synapse state from the synapse memory cell, the read line being used for reading one of the first set of the predetermined number of states from all of the plural cell components simultaneously.
    Type: Application
    Filed: November 9, 2016
    Publication date: May 10, 2018
    Inventors: Kohji Hosokawa, Masatoshi Ishii, Takeo Yasuda
  • Publication number: 20170344885
    Abstract: Methods and systems are provided for operating a neuromorphic system for generating neuron and synapse activities. The method includes: preparing at least one digital timer in the neuromorphic system, each of the at least one digital timers including multi-bit digital values; generating time signals using the at least one digital timer; emulating an analog waveform of a neuron spike; updating parameters of the neuromorphic system using the time signals and the current values of the parameters; presetting, using a processor, the digital values of the at least one digital timer to initial values when the spike input is provided to the node; and updating, using the processor, the digital values of the at least one digital timer with a specified amount when there is an absence of a spike input to the node.
    Type: Application
    Filed: May 31, 2016
    Publication date: November 30, 2017
    Inventors: Kohji Hosokawa, Masatoshi Ishii, Yutaka Nakamura, Junka Okazawa, Takeo Yasuda
  • Publication number: 20170255860
    Abstract: Embodiments include methods and systems of neuron leaky integrate and fire circuit (NLIFC). Aspects include: receiving an input current having both AC component and DC component at an input terminal of the NLIFC, extracting AC component of input current, generating a number of swing voltages at a swing node using extracted AC component of the input current, transferring charge from a pull-up node to a neuron membrane potential (NP) node through an integration diode and a pull-up diode to raise a voltage at NP node over an integration capacitor gradually and the voltage at NP node shows integration value of AC component of input current, implementing leaky decay function of the neuron leaky integrate and fire circuit, detecting a timing of neuron fire using an analog comparator, resetting a neuron membrane potential level for a refractory period after neuron fire, and generating fire output signal of the NLIFC.
    Type: Application
    Filed: March 3, 2016
    Publication date: September 7, 2017
    Inventors: Mark B. Ritter, Takeo Yasuda
  • Publication number: 20170243108
    Abstract: Embodiments are directed to a driver circuit including a first amplifier having a voltage follower configured to control a first node to maintain a voltage of the first node at a constant value. By maintaining the first node voltage, the first amplifier having the voltage follower is further configured to have a first amplifier output current into the first node at a value without the effect of the voltage fluctuation. The driver circuit further includes a second amplifier configured to control a second node, wherein the second amplifier is in a current mirror configuration with respect to the first amplifier such that a second amplifier current output is a highly precise mirror of the first amplifier current output.
    Type: Application
    Filed: February 19, 2016
    Publication date: August 24, 2017
    Inventors: Mark B. Ritter, Takeo Yasuda
  • Publication number: 20170185890
    Abstract: Described is a neuromorphic system implemented in hardware that implements neuron membrane potential update based on the leaky integrate and fire (LIF) model. The system further models synapse weights update based on the spike time-dependent plasticity (STDP) model. The system includes an artificial neural network in which the update scheme of neuron membrane potential and synapse weight are effectively defined and implemented.
    Type: Application
    Filed: December 28, 2015
    Publication date: June 29, 2017
    Inventors: Takeo Yasuda, Kohji Hosokawa, Yutaka Nakamura, Junka Okazawa, Masatoshi Ishii
  • Publication number: 20170185889
    Abstract: A method and system are provided for updating synapse weight values in neuromorphic system with Spike Time Dependent Plasticity model. The method includes selectively performing, by a hardware-based synapse weight incrementer or decrementer, one of a synapse weight increment function or decrement function, each using a respective lookup table, to generate updated synapse weight values responsive to spike timing data. The method further includes storing the updated synapse weight values in a memory. The method additionally includes performing, by a hardware-based processor, a learning process to integrate the updated synapse weight values stored in the memory into the Spike Time Dependent Plasticity model neuromorphic system for improved neuromorphic simulation.
    Type: Application
    Filed: December 28, 2015
    Publication date: June 29, 2017
    Inventors: Kohji Hosokawa, Masatoshi Ishii, Yutaka Nakamura, Junka Okazawa, Takeo Yasuda
  • Publication number: 20170185891
    Abstract: A method and system are provided for updating a neuron membrane potential in a spike time dependent plasticity model in a Neuromorphic system. The method includes approximating a shape of an analog spike signal from an axon input using a hardware-based digital axon timer. The method further includes generating a first intermediately updated neuron membrane potential value from a current axon timer value, a current synapse weight value and a current neuron membrane potential value using a first look-up table and an accumulator. The method also includes generating a second intermediately updated neuron membrane potential value with a leak decay effect using a second look-up table and the first intermediately updated neuron membrane potential value. The method additionally includes generating a final updated neuron membrane potential value based on a comparison of the second intermediately updated neuron membrane potential value with a neuron fire threshold level using a comparator.
    Type: Application
    Filed: December 28, 2015
    Publication date: June 29, 2017
    Inventors: Kohji Hosokawa, Masatoshi Ishii, Yutaka Nakamura, Junka Okazawa, Takeo Yasuda
  • Publication number: 20170047911
    Abstract: A pulse generator and a method of fabricating a pulse generator are described. The pulse generator includes an input node to receive an input voltage, a first capacitor, and a second capacitor. The first capacitor is positioned between the input node and the second capacitor. An output node outputs an output voltage with a pulse shape, and the pulse generator also includes at least one switch between the input node and the second capacitor. The at least one switch controls the pulse shape of the output voltage.
    Type: Application
    Filed: November 23, 2015
    Publication date: February 16, 2017
    Inventors: Kohji Hosokawa, Masatoshi Ishii, Mark B. Ritter, Takeo Yasuda