Patents by Inventor Takeshi Akatsu
Takeshi Akatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220143613Abstract: There is provided a biomolecule collection device, comprising: a fluid chamber having a plurality of inner walls; and a plurality of nanowires disposed on two or more inner walls of the plurality of inner walls of the fluid chamber.Type: ApplicationFiled: January 29, 2020Publication date: May 12, 2022Inventors: Ryuichi ONOSE, Takeshi AKATSU
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Publication number: 20190071720Abstract: The present disclosure provides devices, systems and methods for sequencing nucleic acid molecules. A sequence of a nucleic acid molecule may be identified at high accuracy using a chip comprising an array of sensors, wherein each individual sensor comprises at least one nano-gap electrode pair configured to generate electrical signals upon flow of the nucleic acid molecule through or in proximity to at least one nano-gap of the nano-gap electrode pair.Type: ApplicationFiled: March 27, 2018Publication date: March 7, 2019Inventors: Eric S. Nordman, Mark Oldham, Takeshi Akatsu
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Publication number: 20110233733Abstract: The invention relates to a release substrate produced from semiconductor materials, and which includes a first substrate release layer having a surface in contact with a connecting layer, and a second substrate release layer having a surface in contact with the connecting layer opposite the first substrate release layer so that the connecting layer is located between the first substrate release layer and second substrate release layer; and a concentrated zone of solid nanoparticles located within the connecting layer to maintain the bonding energy of the reversible connection substantially constant even when the substrate is exposed to heat treatment while also facilitating breaking of the connecting layer by mechanical action.Type: ApplicationFiled: June 2, 2011Publication date: September 29, 2011Inventors: Olivier Rayssac, Pierre Rayssac, Gisèle Rayssac, Takeshi Akatsu
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Patent number: 8012289Abstract: The invention relates to a method of fabricating a release substrate produced from semiconductor materials, the method comprising creating a reversible connection between two substrate release layers characterized in that the reversible connection is formed by a connecting layer produced using a first material as the basis, the connecting layer further comprising a nanoparticle concentrating zone of a second material disposed to facilitate release of the substrate, the first and second materials being selected to maintain the bonding energy of the reversible connection substantially constant even when the substrate is exposed to heat treatment.Type: GrantFiled: February 25, 2009Date of Patent: September 6, 2011Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Olivier Rayssac, Pierre Rayssac, legal representative, Gisèle Rayssac, legal representative, Takeshi Akatsu
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Patent number: 7776716Abstract: A method for fabricating semiconductor on insulator wafers by providing a semiconductor substrate or a substrate that includes an epitaxial semiconductor layer as a source substrate, attaching the source substrate to a handle substrate to form a source handle assembly and detaching the source substrate at a predetermined splitting area provided inside the source substrate and being essentially parallel to its main surface, to remove a layer from the source handle assembly to thereby create the semiconductor on insulator wafer. A diffusion barrier layer, in particular, an oxygen diffusion barrier layer can be provided on the source substrate. In addition the invention relates to the corresponding semiconductor on insulator wafers that are produced by the method.Type: GrantFiled: May 9, 2007Date of Patent: August 17, 2010Assignees: S.O.I.Tec Silicon on Insulator Technologies, Commissariat à l'Energie Atomique (CEA)Inventors: Chrystel Deguet, Takeshi Akatsu, Hubert Moriceau, Thomas Signamarcheix, Loic Sanchez
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Publication number: 20100167500Abstract: A method for forming a semiconductor structure that includes a thin layer of semiconductor material on a receiver wafer is disclosed. The method includes removing a thickness of material from a donor wafer, which comprises a support substrate and an epitaxial layer, for surface preparation and transferring a portion of the epitaxial layer from the donor wafer to the receiver wafer. The thickness removed during the surface preparation is adapted to enable formation of a new semiconductor structure from the remaining epitaxial portion of the donor wafer.Type: ApplicationFiled: March 5, 2010Publication date: July 1, 2010Inventors: Nabil Chhaimi, Eric Guiot, Patrick Reynaud, Bruno Ghyselen, Cécile Aulnette, Bénédite Osternaud, Takeshi Akatsu, Yves-Matthieu Le Vaillant
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Publication number: 20090325362Abstract: A method for forming a semiconductor structure that includes a thin layer of semiconductor material on a receiver wafer is disclosed. The method includes removing a thickness of material from a donor wafer, which comprises a support substrate and an epitaxial layer, for surface preparation and transferring a portion of the epitaxial layer from the donor wafer to the receiver wafer. The thickness removed during the surface preparation is adapted to enable formation of a new semiconductor structure from the remaining epitaxial portion of the donor wafer.Type: ApplicationFiled: July 15, 2009Publication date: December 31, 2009Inventors: Nabil Chhaimi, Eric Guiot, Patrick Reynaud, Bruno Ghyselen, Cécile Aulnette, Bénédicte Osternaud, Takeshi Akatsu, Bruce Faure
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Patent number: 7602046Abstract: The invention relates to a recyclable donor wafer that includes a substrate and a formed layer thereon, wherein the formed layer has a thickness sufficient to provide (a) at least two useful layers for detachment therefrom and (b) additional material that can be removed to planarize exposed surfaces of the useful layers prior to detachment from the donor wafer.Type: GrantFiled: March 7, 2005Date of Patent: October 13, 2009Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Bruno Ghyselen, Cécile Aulnette, Bénédite Osternaud, Takeshi Akatsu, Bruce Faure
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Publication number: 20090179299Abstract: The invention relates to a method of fabricating a release substrate produced from semiconductor materials, the method comprising creating a reversible connection between two substrate release layers characterized in that the reversible connection is formed by a connecting layer produced using a first material as the basis, the connecting layer further comprising a nanoparticle concentrating zone of a second material disposed to facilitate release of the substrate, the first and second materials being selected to maintain the bonding energy of the reversible connection substantially constant even when the substrate is exposed to heat treatment.Type: ApplicationFiled: February 25, 2009Publication date: July 16, 2009Inventors: Olivier RAYSSAC, Takeshi Akatsu
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Patent number: 7544265Abstract: The invention relates to a method of fabricating a release substrate produced from semiconductor materials, the method comprising creating a reversible connection between two substrate release layers characterized in that the reversible connection is formed by a connecting layer produced using a first material as the basis, the connecting layer further comprising a nanoparticle concentrating zone of a second material disposed to facilitate release of the substrate, the first and second materials being selected to maintain the bonding energy of the reversible connection substantially constant even when the substrate is exposed to heat treatment.Type: GrantFiled: July 5, 2006Date of Patent: June 9, 2009Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Pierre Rayssac, legal representative, Gisele Rayssac, legal representative, Takeshi Akatsu, Olivier Rayssac
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Patent number: 7476930Abstract: The invention concerns a field-effect transistor with a drain, a source, a channel in electrical contact with the source and the drain, and at least one gate, so as to apply an electric field to the channel when each gate is polarized, where the channel has a multi-layer structure with at least three layers, and with at least one of the layers of the multi-layer structure having electrical properties that are substantially different from those of another layer of the multi-layer structure, and wherein a single gate or two gates are arranged substantially perpendicular to a reference plane of the channel defined by an interface plane between two layers of the multi-layer structure.Type: GrantFiled: July 5, 2007Date of Patent: January 13, 2009Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Fréderic Allibert, Takeshi Akatsu, Bruno Ghyselen
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Patent number: 7449394Abstract: Methods for forming a semiconductor structure are described. In an embodiment, the technique includes providing a donor wafer having a first semiconductor layer and a second semiconductor layer on the first layer and having a free surface; coimplanting two different atomic species through the free surface of the second layer to form a zone of weakness zone in the first layer; bonding the free surface of the second layer to a host wafer; and supplying energy to detach at the zone of weakness a semiconductor structure comprising the host wafer, the second layer and a portion of the first layer.Type: GrantFiled: July 11, 2005Date of Patent: November 11, 2008Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Takeshi Akatsu, Nicolas Daval, Nguyet-Phuong Nguyen, Olivier Rayssac, Konstantin Bourdelle
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Patent number: 7378729Abstract: A donor wafer resulting from a method of recycling the wafer after detaching at least one useful layer. The donor wafer includes a substrate; a buffer structure on the substrate; a protective layer associated with the buffer structure; and a post detachment layer located above the buffer structure and presenting projections or rough portions on its surface. The protective layer prevents removal of the entire buffer structure when the post detachment layer is removed.Type: GrantFiled: November 23, 2005Date of Patent: May 27, 2008Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Bruno Ghyselen, Cécile Aulnette, Bénédite Osternaud, Yves-Mathieu Le Vaillant, Takeshi Akatsu
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Patent number: 7375008Abstract: The invention relates to a method of re-forming a useful layer on a donor wafer after taking off a useful layer formed of a material chosen from among semiconductor materials. The donor wafer includes in succession a substrate and a taking-off structure, the taking-off structure includes the taken-off useful layer before taking-off. The method includes a removal of material involving a portion of the donor wafer on the side where the useful layer has been taken off. The material is removed by mechanical means so as to preserve a portion of the taking-off structure to form at least one other useful layer which can be taken off after re-forming, without adding additional material to the wafer.Type: GrantFiled: March 7, 2005Date of Patent: May 20, 2008Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Bruno Ghyselen, Cécile Aulnette, Bénédite Osternaud, Takeshi Akatsu, Bruce Faure
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Patent number: 7326628Abstract: A method for producing a semiconductor structure by conducting controlled co-implanting of at least first and second different atomic species into a donor substrate to create an embrittlement zone which defines a thin layer of donor material to be transferred. Implantation energies are selected so that the first and second species are respectively distributed in the donor wafer according to a repartition profile that presents a spreading zone in which each species is mainly distributed at a maximum concentration peak. The implantation doses and energies of the first and second species are selected such that the second species is implanted deeper in the embrittlement zone than the first species spreading zone. The donor substrate is detached at the embrittlement zone to transfer the thin layer to the support substrate while minimizing blister formation in and surface roughness of the transferred layer.Type: GrantFiled: July 13, 2005Date of Patent: February 5, 2008Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Nadia Ben Mohamed, Nguyet-Phuong Nguyen, Takeshi Akatsu, Alice Boussagol, Gabriela Suciu
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Patent number: 7323398Abstract: A method of manufacturing a crystalline wafer that includes implanting first atomic species in a donor substrate to form a region of weakness at a first depth therein and configured to facilitate detachment of a first layer of the donor substrate from a remaining portion of the donor substrate. The first layer and remaining portion are disposed on opposite sides of the region of weakness. The method also includes implanting second atomic species in the donor substrate to form a gettering region at a second depth therein that is different than the first depth to reduce or minimize migration of the implanted first atomic species past the gettering region. This reduces or minimizes an increase in roughness of a surface produced on the first layer after detachment thereof from the remaining portion at the region of weakness.Type: GrantFiled: September 20, 2005Date of Patent: January 29, 2008Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventor: Takeshi Akatsu
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Publication number: 20070284660Abstract: A method for fabricating semiconductor on insulator wafers by providing a semiconductor substrate or a substrate that includes an epitaxial semiconductor layer as a source substrate, attaching the source substrate to a handle substrate to form a source handle assembly and detaching the source substrate at a predetermined splitting area provided inside the source substrate and being essentially parallel to its main surface, to remove a layer from the source handle assembly to thereby create the semiconductor on insulator wafer. A diffusion barrier layer, in particular, an oxygen diffusion barrier layer can be provided on the source substrate. In addition the invention relates to the corresponding semiconductor on insulator wafers that are produced by the method.Type: ApplicationFiled: May 9, 2007Publication date: December 13, 2007Inventors: Chrystel Deguet, Takeshi Akatsu, Hubert Moriceau, Thomas Signamarcheix, Loic Sanchez
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Publication number: 20070257301Abstract: The invention concerns a field-effect transistor with a drain, a source, a channel in electrical contact with the source and the drain, and at least one gate, so as to apply an electric field to the channel when each gate is polarised, where the channel has a multi-layer structure with at least three layers, and with at least one of the layers of the multi-layer structure having electrical properties that are substantially different from those of another layer of the multi-layer structure, and wherein a single gate or two gates are arranged substantially perpendicular to a reference plane of the channel defined by an interface plane between two layers of the multi-layer structure.Type: ApplicationFiled: July 5, 2007Publication date: November 8, 2007Inventors: Frederic Allibert, Takeshi Akatsu, Bruno Ghyselen
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Patent number: 7285495Abstract: A method for thermally treating a semiconductor layer is described. An embodiment of the technique includes implanting atomic species into a first surface of a donor wafer to form a zone of weakness at a predetermined depth that defines the thickness of a transfer layer, bonding the first surface of the donor wafer to a host wafer, supplying energy to detach the transfer layer from the donor wafer at the zone of weakness, and conducting a recovery operation on the transfer layer. The recovery operation is conducted after detachment but while the layer remains in contact with the donor wafer. The recovery operation includes heat treating the transfer layer for a predetermined duration at a recovery temperature that is lower than a re-adhesion temperature at which the transfer layer would re-adhere to the donor wafer, to improve the crystalline quality and the surface roughness of the transfer layer.Type: GrantFiled: February 16, 2005Date of Patent: October 23, 2007Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Nicolas Daval, Takeshi Akatsu, Nguyet-Phuong Nguyen
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Patent number: 7282449Abstract: A method for thermally treating a silicon germanium semiconductor layer from a donor wafer is described. An embodiment of the technique includes co-implanting atomic species into a first surface of the donor wafer to form a zone of weakness at a predetermined depth that defines the thickness of a transfer layer, bonding the first surface of the donor wafer to a host wafer, supplying energy to detach the transfer layer from the donor wafer at the zone of weakness, and conducting a recovery operation on the transfer layer. The recovery operation is conducted after detachment but while the layer remains in contact with the donor wafer. The recovery operation includes heat treating the transfer layer for a predetermined duration at a recovery temperature that is lower than a re-adhesion temperature at which the transfer layer would re-adhere to the donor wafer, to improve the crystalline quality and the surface roughness of the transfer layer.Type: GrantFiled: February 17, 2006Date of Patent: October 16, 2007Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Nicolas Daval, Takeshi Akatsu, Nguyet-Phuong Nguyen