Patents by Inventor Takeshi Akatsu
Takeshi Akatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7276428Abstract: Methods for forming a semiconductor structure are described. In an embodiment, the technique includes providing a donor wafer having a first semiconductor layer and a second semiconductor layer on the first layer and having a free surface, implanting atomic species through the free surface of the second layer to form a zone of weakness zone in the first layer, and bonding the free surface of the second layer to a host wafer. The method also includes supplying energy to detach at the zone of weakness a semiconductor structure comprising the host wafer, the second layer and a portion of the first layer, conducting a bond strengthening step on the structure after detachment at a temperature of less than about 800° C. to improve the strength of the bond between the second layer and the host wafer, and selectively etching the first layer portion to remove it from the structure and to expose a surface of the second layer.Type: GrantFiled: February 16, 2005Date of Patent: October 2, 2007Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Nicolas Daval, Takeshi Akatsu, Nguyet-Phuong Nguyen, Olivier Rayssac
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Patent number: 7265435Abstract: A method for implanting atomic species through an uneven surface of a semiconductor layer. The technique includes applying a covering layer upon the uneven surface in an amount sufficient and in a manner to increase surface uniformity. The method also includes implanting atomic species through the covering layer and uneven surface to obtain a more uniform depth of implantation of the atomic species in the layer.Type: GrantFiled: October 31, 2005Date of Patent: September 4, 2007Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Bruno Ghyselen, Takeshi Akatsu
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Patent number: 7256075Abstract: The invention relates to a method of transferring useful layers from a donor wafer which includes a multi-layer structure on the surface of the donor wafer that has a thickness sufficient to form multiple useful layers for subsequent detachment. The layers may be formed of materials having sufficiently different properties such that they may be selectively removed. The layers of material may also include sub-layers that can be selectively removed from each other.Type: GrantFiled: March 7, 2005Date of Patent: August 14, 2007Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Bruno Ghyselen, Cécile Aulnette, Bénédite Osternaud, Takeshi Akatsu, Yves Mathieu Le Vaillant
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Patent number: 7232488Abstract: The present invention relates to a method of fabrication of a substrate for an epitaxial growth. A relaxed epitaxial base layer is obtained on an auxiliary substrate. The invention allows the fabrication of substrates with a more efficient epitaxial growth of a material with a desired lattice parameter on another material with a different lattice parameter. The material can be grown with a high thermodynamic and crystallographic stability. At least a part of the epitaxial base layer is transferred onto a carrier substrate, forming a base substrate, and growing the material of the epitaxial base layer is further grown on the carrier substrate.Type: GrantFiled: April 20, 2004Date of Patent: June 19, 2007Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Takeshi Akatsu, Cecile Aulnette, Bruno Ghyselen
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Publication number: 20070077729Abstract: The invention relates to a method of fabricating a release substrate produced from semiconductor materials, the method comprising creating a reversible connection between two substrate release layers characterized in that the reversible connection is formed by a connecting layer produced using a first material as the basis, the connecting layer further comprising a nanoparticle concentrating zone of a second material disposed to facilitate release of the substrate, the first and second materials being selected to maintain the bonding energy of the reversible connection substantially constant even when the substrate is exposed to heat treatment.Type: ApplicationFiled: July 5, 2006Publication date: April 5, 2007Inventors: Olivier Rayssac, Takeshi Akatsu, Pierre Rayssac, Gisele Rayssac
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Publication number: 20060141748Abstract: A method for thermally treating a silicon germanium semiconductor layer from a donor wafer is described. An embodiment of the technique includes co-implanting atomic species into a first surface of the donor wafer to form a zone of weakness at a predetermined depth that defines the thickness of a transfer layer, bonding the first surface of the donor wafer to a host wafer, supplying energy to detach the transfer layer from the donor wafer at the zone of weakness, and conducting a recovery operation on the transfer layer. The recovery operation is conducted after detachment but while the layer remains in contact with the donor wafer. The recovery operation includes heat treating the transfer layer for a predetermined duration at a recovery temperature that is lower than a re-adhesion temperature at which the transfer layer would re-adhere to the donor wafer, to improve the crystalline quality and the surface roughness of the transfer layer.Type: ApplicationFiled: February 17, 2006Publication date: June 29, 2006Inventors: Nicolas Daval, Takeshi Akatsu, Nguyet-Phuong Nguyen
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Patent number: 7033905Abstract: A method of recycling a donor wafer after detaching at least one useful layer is provided, the donor wafer comprising successively a substrate, a buffer structure and, before detachment, a useful layer. The method comprises employing mechanical means to remove part of the donor wafer on the side where the detachment took place, such that, after removal of substance, there remains at least part of the buffer structure capable of being reused as at least part of a buffer structure during a subsequent detachment of a useful layer. The present document also relates to methods of detaching a thin layer from a donor wafer which can be recycled according to the invention, as well as donor wafers which can be recycled in accordance with the invention.Type: GrantFiled: December 1, 2003Date of Patent: April 25, 2006Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.Inventors: Bruno Ghyselen, Cécile Aulnette, Bénédite Osternaud, Yves-Mathieu Vaillant, Takeshi Akatsu
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Publication number: 20060076578Abstract: A donor wafer resulting from a method of recycling the wafer after detaching at least one useful layer. The donor wafer includes a substrate; a buffer structure on the substrate; a protective layer associated with the buffer structure; and a post detachment layer located above the buffer structure and presenting projections or rough portions on its surface. The protective layer prevents removal of the entire buffer structure when the post detachment layer is removed.Type: ApplicationFiled: November 23, 2005Publication date: April 13, 2006Applicant: S.O.I.Tec Silicon on Insulator Technologies S.A.Inventors: Bruno Ghyselen, Cecile Aulnette, Benedite Osternaud, Yves-Mathieu Le Vaillant, Takeshi Akatsu
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Patent number: 7018913Abstract: A method for implanting atomic species through an uneven surface of a semiconductor layer. The technique includes applying a covering layer upon the uneven surface in an amount sufficient and in a manner to increase surface uniformity. The method also includes implanting atomic species through the covering layer and uneven surface to obtain a more uniform depth of implantation of the atomic species in the layer.Type: GrantFiled: May 5, 2004Date of Patent: March 28, 2006Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.Inventors: Bruno Ghyselen, Takeshi Akatsu
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Publication number: 20060063353Abstract: A method of manufacturing a crystalline wafer that includes implanting first atomic species in a donor substrate to form a region of weakness at a first depth therein and configured to facilitate detachment of a first layer of the donor substrate from a remaining portion of the donor substrate. The first layer and remaining portion are disposed on opposite sides of the region of weakness. The method also includes implanting second atomic species in the donor substrate to form a gettering region at a second depth therein that is different than the first depth to reduce or minimize migration of the implanted first atomic species past the gettering region. This reduces or minimizes an increase in roughness of a surface produced on the first layer after detachment thereof from the remaining portion at the region of weakness.Type: ApplicationFiled: September 20, 2005Publication date: March 23, 2006Inventor: Takeshi Akatsu
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Publication number: 20060060943Abstract: The invention relates to a method for producing a semiconductor structure which comprises conducting controlled co-implanting of at least first and second different atomic species into a face of donor substrate to create an embrittlement zone which defines a thin layer of donor material to be transferred. This step is conducted by selecting implantation energies so that the coimplanting is made under conditions such that the first and second species are respectively distributed in the donor wafer according to a repartition profile that presents a spreading zone in which each species is mainly distributed and at a maximum concentration peak.Type: ApplicationFiled: July 13, 2005Publication date: March 23, 2006Inventors: Nadia Ben Mohamed, Nguyet-Phuong Nguyen, Takeshi Akatsu, Alice Boussagol, Gabriela Suciu
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Publication number: 20060051944Abstract: A method for implanting atomic species through an uneven surface of a semiconductor layer. The technique includes applying a covering layer upon the uneven surface in an amount sufficient and in a manner to increase surface uniformity. The method also includes implanting atomic species through the covering layer and uneven surface to obtain a more uniform depth of implantation of the atomic species in the layer.Type: ApplicationFiled: October 31, 2005Publication date: March 9, 2006Applicant: S.O.I. Tec Silicon on Insulator Technologies S.A., a French companyInventors: Bruno Ghyselen, Takeshi Akatsu
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Patent number: 7008857Abstract: A method of recycling a donor wafer after detaching at least one useful layer is provided, the donor wafer comprising successively a substrate, a buffer structure and, before detachment, a useful layer. The method includes removal of substance relating to part of the donor wafer on the side where the detachment took place, such that, after removal of substance, there remains at least part of the buffer structure capable of being reused as at least part of a buffer structure during a subsequent detachment of a useful layer. The present document also relates to a method of producing a donor wafer which can be recycled according to the invention, methods of detaching a thin layer from a donor wafer which can be recycled according to the invention, and donor wafers which can be recycled according to the invention.Type: GrantFiled: January 23, 2004Date of Patent: March 7, 2006Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.Inventors: Bruno Ghyselen, Cécile Aulnette, Bénédite Osternaud, Yves-Mathieu Vaillant, Takeshi Akatsu
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Patent number: 7001826Abstract: A process for forming a useful layer (6) from a wafer (10), the wafer (10) comprising a supporting substrate (1) and a strained layer (2) that are chosen respectively from crystalline materials. The process includes a first step of forming a region of perturbation (3) in the supporting substrate (1) at a defined depth by creating structural perturbations that cause at least relative relaxation of the elastic strains in the strained layer (2). A second step of supplying energy causes at least relative relaxation of the elastic strains in the strained layer (2). A portion of the wafer (10) is removed from the opposite side from the relaxed strained layer (2?), the useful layer (6) being the remaining portion of the wafer (10). The present invention also relates to an application of the process and to wafers produced during the process.Type: GrantFiled: September 17, 2003Date of Patent: February 21, 2006Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.Inventors: Takeshi Akatsu, Bruno Ghyselen
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Publication number: 20060030087Abstract: The present invention relates to a compliant substrate having a top surface for receiving a heteroepitaxial structure or heteroepitaxial layer. This substrate comprises a carrier substrate, a top single-crystalline layer, a buried layer located between the carrier substrate and the top layer, and a weakened region located in the top layer or between the top layer and the buried layer such that the compliant substrate facilitates relaxed growth of a heteroepitaxial layer or structure upon the top surface. The invention also relates to the combination of the compliant substrate and a heteroepitaxial layer provided thereon, as well as to a method of making the compliant substrate and combination.Type: ApplicationFiled: September 13, 2005Publication date: February 9, 2006Inventor: Takeshi Akatsu
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Publication number: 20060014363Abstract: A method for forming a structure that includes a layer that is removed from a donor wafer that has a first layer made of a semiconductor material containing germanium. The method includes the steps of forming a weakness zone in the thickness of the first layer; bonding the donor wafer to a host wafer; and supplying energy so as to weaken the donor wafer at the level of the zone of weakness. The zone of weakness is formed by subjecting the donor wafer to a co-implantation of at least two different atomic species, while the bonding is carried out by performing a thermal treatment at a temperature between 300° C. and 400° C. for a duration of from 30 minutes to four hours.Type: ApplicationFiled: September 21, 2005Publication date: January 19, 2006Inventors: Nicolas Daval, Takeshi Akatsu, Nguyet-Phuong Nguyen, Olivier Rayssac, Konstantin Bourdelle
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Patent number: 6982210Abstract: A method for manufacturing a multilayer semiconductor structure that includes an irregular layer. In an embodiment, the method includes providing a layer of irregular material on a donor substrate. The irregular layer has a flat face at an interface with the donor substrate, and has an opposite, irregular face. Next; a weakened zone is created at a predetermined depth within the donor substrate. An intermediate layer of material is then provided that covers the irregular face of the irregular layer, the intermediate layer providing a substantially flat surface. The substantially flat surface of the intermediate layer is then bonded to a receiver substrate, and the donor substrate is detached along the weakened zone to form the multilayer semiconductor structure. The multilayer structure includes an useful layer, the irregular layer, the intermediate layer and the receiver substrate, wherein all of the irregular material of the irregular layer is present in the structure.Type: GrantFiled: December 3, 2003Date of Patent: January 3, 2006Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.Inventors: Bruno Ghyselen, Takeshi Akatsu
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Publication number: 20050245049Abstract: Methods for forming a semiconductor structure are described. In an embodiment, the technique includes providing a donor wafer having a first semiconductor layer and a second semiconductor layer on the first layer and having a free surface; coimplanting two different atomic species through the free surface of the second layer to form a zone of weakness zone in the first layer; bonding the free surface of the second layer to a host wafer; and supplying energy to detach at the zone of weakness a semiconductor structure comprising the host wafer, the second layer and a portion of the first layer.Type: ApplicationFiled: July 11, 2005Publication date: November 3, 2005Inventors: Takeshi Akatsu, Nicolas Daval, Nguyet-Phuong Nguyen, Olivier Rayssac, Konstantin Bourdelle
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Publication number: 20050196937Abstract: Methods for forming a semiconductor structure are described. In an embodiment, the technique includes providing a donor wafer having a first semiconductor layer and a second semiconductor layer on the first layer and having a free surface, implanting atomic species through the free surface of the second layer to form a zone of weakness zone in the first layer, and bonding the free surface of the second layer to a host wafer. The method also includes supplying energy to detach at the zone of weakness a semiconductor structure comprising the host wafer, the second layer and a portion of the first layer, conducting a bond strengthening step on the structure after detachment at a temperature of less than about 800° C. to improve the strength of the bond between the second layer and the host wafer, and selectively etching the first layer portion to remove it from the structure and to expose a surface of the second layer.Type: ApplicationFiled: February 16, 2005Publication date: September 8, 2005Inventors: Nicolas Daval, Takeshi Akatsu, Nguyet-Phuong Nguyen, Olivier Rayssac
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Publication number: 20050196936Abstract: A method for thermally treating a semiconductor layer is described. An embodiment of the technique includes implanting atomic species into a first surface of a donor wafer to form a zone of weakness at a predetermined depth that defines the thickness of a transfer layer, bonding the first surface of the donor wafer to a host wafer, supplying energy to detach the transfer layer from the donor wafer at the zone of weakness, and conducting a recovery operation on the transfer layer. The recovery operation is conducted after detachment but while the layer remains in contact with the donor wafer. The recovery operation includes heat treating the transfer layer for a predetermined duration at a recovery temperature that is lower than a re-adhesion temperature at which the transfer layer would re-adhere to the donor wafer, to improve the crystalline quality and the surface roughness of the transfer layer.Type: ApplicationFiled: February 16, 2005Publication date: September 8, 2005Inventors: Nicolas Daval, Takeshi Akatsu, Nguyet-Phuong Nguyen