Abstract: In a data holding mode, data storage in a one bit/one cell scheme in a normal operating mode are rearranged into data storage in a twin-cell mode in which data are stored in a one bit/two cell scheme. In the twin-cell mode, two sub word lines are simultaneously driven into a selected state, and storage data of memory cells are read out on both of bit lines in a pair, to perform a sense operation. Thus, the read-out voltage can be increased to improve the data retention characteristics for lengthening a refresh interval, resulting in a reduced power consumption in the data holding mode.

Abstract: A method for restricting an excessive temperature rise in an internal combustion engine according to the present invention can provide a technology that enable to restrict an excessive temperature rise of a filter more reliably in an internal combustion engine having the filter provided in the exhaust passage for collecting particulate matter in the exhaust gas. In that method, when the running state of the internal combustion engine becomes idle running during the filter regeneration process, the oxygen concentration in the exhaust gas flowing into the filter is reduced. After that, when the running state of the internal combustion engine shifts from the idle running to a running state with an engine load higher than in the idle running, the oxygen concentration in the exhaust gas flowing into the filter is gradually increased.

Abstract: A variable valve timing control device includes a drive member rotatable in synchronization with a crankshaft, a rotatable driven member connected to a camshaft arranged co-axially with the drive member, a hydraulic chamber formed at one of the drive member and the driven member, a vane dividing the hydraulic chamber into an advanced angle chamber and a retarded angle chamber, a relative rotation phase controlling mechanism which controls a relative rotation phase between the drive member and the driven member between a most retarded angle phase in which a volume of the advanced angle chamber is a maximum and a most advanced angle phase in which a volume of the retarded angle chamber is a maximum by supplying or discharging operation fluid to and/or from the advanced angle chamber and the retarded angle chamber, a lock mechanism which restricts relative rotation between the drive member and the driven member, when the relative rotation phase is a predetermined lock phase between the most advanced angle phase

Abstract: A semiconductor integrated circuit includes a memory for holding data a logic circuit inputs or outputs. The memory is composed of logic cells, and is placed in a logic region. Thus, the semiconductor integrated circuit can prevent forming wasted space, in which no circuit component is built, and reduce its area and power consumption. It can reduce the design period of the memory as compared with the case where hard macro cells are used.

Abstract: A NOx catalyst for selectively reducing NOx in exhaust gas by adsorbing ammonia is provided at an exhaust system of an engine, ammonia or urea water is supplied to the NOx catalyst by reducing agent supplying means, a consumption amount of ammonia adsorbed to the NOx catalyst is derived by consumption amount deriving means based on an exhaust amount of NOx exhausted from the engine detected or estimated by NOx exhaust amount deriving means and an actual NOx cleaning rate by the NOx catalyst derived by actual NOx cleaning rate deriving means, an actual adsorption amount of ammonia adsorbed to the NOx catalyst is derived in accordance with an addition amount of ammonia and the consumption amount of ammonia by adsorption amount deriving means and the reducing agent supplying means is controlled by controlling means in accordance with the actual adsorption amount.

Abstract: A variable valve timing control device includes a drive member rotatable in synchronization with a crankshaft, a rotatable driven member connected to a camshaft arranged co-axially with the drive member, a hydraulic chamber formed at one of the drive member and the driven member, a vane dividing the hydraulic chamber into an advanced angle chamber and a retarded angle chamber, a relative rotation phase controlling mechanism which controls a relative rotation phase between the drive member and the driven member between a most retarded angle phase in which a volume of the advanced angle chamber is a maximum and a most advanced angle phase in which a volume of the retarded angle chamber is a maximum by supplying or discharging operation fluid to and/or from the advanced angle chamber and the retarded angle chamber, a lock mechanism which restricts relative rotation between the drive member and the driven member, when the relative rotation phase is a predetermined lock phase between the most advanced angle phase

Abstract: An IP generating system includes an IP (Intellectual Property) providing apparatus and at least one development apparatus. The IP providing apparatus searches for a development apparatus installing a memory compiler to be revised with reference to applied condition data managed by a master database, and transmits the revision information as to the memory compiler to the development apparatus. The system can revise the memory compiler without requiring a user to make a decision as to the necessity of the revision of the memory compiler.

Abstract: A connection verification apparatus verifies interconnection between a plurality of logic blocks constituting a semiconductor integrated circuit or the like. It includes a connection verification section for verifying interconnection between a first logic block and a second logic block by comparing a signal level of an output terminal of the first logic block with a signal level of an input terminal of the second logic block connected to the output terminal of the first logic block. The connection verification apparatus can verify the interconnection between the two logic blocks without verifying the logic processing to the two logic blocks.

Abstract: An exhaust emission control system of an internal combustion engine capable of post injection is disclosed which provides control such that the injection timing in sub injection is set to a point earlier than the target injection timing when the sub injection is started, and the injection timing in the sub injection is then delayed to the target injection timing. This realizes the post injection under the optimum conditions and enables an efficient rise in the exhaust temperature while inhibiting deterioration of the drivability due to a rapid change in torque.

Abstract: An exhaust emission control system of an internal combustion engine is provided which controls the oxygen concentration of exhaust passing through the exhaust emission control device according to the flow rate of exhaust flowing through an exhaust passage when the exhaust emission control device is regenerated, so that the regeneration is completed within a short period of time while the filter is prevented from being damaged by melting during the regeneration. This improves the exhaust emission control performance and reliability of the filter.

Abstract: An NOx catalyst 17 for selectively reducing NOx in exhaust gas by adsorbing ammonia is provided at an exhaust system of an engine 1, ammonia or urea water is supplied to the NOx catalyst by reducing agent supplying means 29, a consumption amount of ammonia adsorbed to the NOx catalyst is derived by consumption amount deriving means 43 based on an exhaust amount of NOx exhausted from the engine detected or estimated by NOx exhaust amount deriving means 41 and an actual NOx cleaning rate by the NOx catalyst derived by actual NOx cleaning rate deriving means 42, an actual adsorption amount of ammonia adsorbed to the NOx catalyst is derived in accordance with an addition amount of ammonia and the consumption amount of ammonia by adsorption amount deriving means 45 and the reducing agent supplying means is controlled by controlling means 46 in accordance with the actual adsorption amount.

Abstract: In a data holding mode, data storage in a one bit/one cell scheme in a normal operating mode are rearranged into data storage in a twin-cell mode in which data are stored in a one bit/two cell scheme. In the twin-cell mode, two sub word lines are simultaneously driven into a selected state, and storage data of memory cells are read out on both of bit lines in a pair, to perform a sense operation. Thus, the read-out voltage can be increased to improve the data retention characteristics for lengthening a refresh interval, resulting in a reduced power consumption in the data holding mode.

Abstract: In a semiconductor integrated circuit device supporting a boundary scan test, the state of an I/O cell is set under the control of a DC test control circuit through a boundary scan register utilized for the boundary scan test for setting an external terminal connected with a pad in a desired state. A semiconductor integrated circuit device allowing execution of a DC test without increasing the circuit area and signal propagation delay is provided.

Abstract: A semiconductor memory includes a redundant RAM disposed independently of at least one regular RAM, the redundant RAM having redundant memory elements by which defective memory elements of the regular RAM can be replaced, and a control block for selecting either at least the regular RAM or the redundant RAM according to an address applied thereto, and for reading data from a memory cell of the selected RAM specified by the address. A plurality of regular RAMs can be disposed and the redundant RAM includes redundant memory elements by which defective memory elements of an arbitrary one of the plurality of regular RAMs can be replaced. The control block selects either one of the plurality of regular RAMs or the redundant RAM according to an address applied thereto, and reads data from a memory cell of the selected RAM specified by the address.

Abstract: A semiconductor intellectual property distribution system includes a registration IP database in which an IP specification of IP is registered, a required IP database storing a required IP specification, a master database storing design information defined by the IP specification and the required IP specification, an evaluation database storing evaluation information related to the registered IP, and a public database storing IP information and the required IP specification that can be made public. When the IP user uses the IP, the semiconductor manufacturer returns a portion of the IP usage charge collected from the IP user.

Abstract: An exhaust emission control system of an internal combustion engine is provided which controls the oxygen concentration of exhaust passing through the exhaust emission control device according to the flow rate of exhaust flowing through an exhaust passage when the exhaust emission control device is regenerated, so that the regeneration is completed within a short period of time while the filter is prevented from being damaged by melting during the regeneration. This improves the exhaust emission control performance and reliability of the filter.

Abstract: An exhaust emission control system of an internal combustion engine capable of post injection is disclosed which provides control such that the injection timing in sub injection is set to a point earlier than the target injection timing when the sub injection is started, and the injection timing in the sub injection is then delayed to the target injection timing. This realizes the post injection under the optimum conditions and enables an efficient rise in the exhaust temperature while inhibiting deterioration of the drivability due to a rapid change in torque.

Abstract: In a data holding mode, data storage in a one bit/one cell scheme in a normal operating mode are rearranged into data storage in a twin-cell mode in which data are stored in a one bit/two cell scheme. In the twin-cell mode, two sub word lines are simultaneously driven into a selected state, and storage data of memory cells are read out on both of bit lines in a pair, to perform a sense operation. Thus, the read-out voltage can be increased to improve the data retention characteristics for lengthening a refresh interval, resulting in a reduced power consumption in the data holding mode.

Abstract: A semiconductor integrated circuit device comprises a memory cell unit, and a data latch unit for temporarily latching write data, which is written into the memory cell unit by way of a normal port. A comparator reads the data, which has been written into the memory cell unit by way of the normal port, from the memory cell unit by way of a test port, and then compares the read data with the original write data latched by the data latch unit. When the comparator detects a mismatch between them, a redundant unit latches the write data to take the place of the memory cell unit and an address holding unit latches information on an address identifying a location of the memory cell unit into which the write data has been written.

Abstract: In a synchronous serial transfer apparatus, the number of lines which are necessary for a serial transfer is reduced, and even when a master/slave operation is to be performed, a serial transfer is possible between any communication apparatuses without using communication apparatuses which have different structures from each other such as a master and slave apparatuses and without using a master apparatus. Communication apparatuses (TR1 to TR3) are connected parallel to each other by one communication line (TRL). A potential fixing apparatus (VC), which fixes a potential on the communication line (TRL) to "High" or "Low" when outputs from all communication apparatuses (TR1 to TR3) are in a "High-Z" state, is connected to the communication line (TRL).