Abstract: An integrated circuit device is structured by a plurality of functional modules (2a, 2b) each performing a predetermined function, each functional module including a test circuit (3) for testing the corresponding module. Each test circuit comprises a scan path (3a-3d) for receiving test data from a single common input line to perform a test and outputting a test output, a tri-state buffer (4a) for controlling an output of the test output from the scan path to a single common output line, and a scan path selecting circuit (5a) for selectively driving the tri-state buffer. All the selecting circuits in the integrated circuit device are connected in series to constitute as a whole a shift register. A selecting signal of the serial data is inputted to the shift register, so that the test output of each scan path is selectively supplied to the common output line.

Abstract: A plurality of bypass scan paths are provided in series between an SI terminal and an SO terminal to constitute a scan path for propagating serial data. In each of bypass scan paths, a selection data propagation holding register and a mode data propagation holding register are not connected in series with a scan register as in a conventional scan path, but arranged on a bypass path formed by a bypass line. Therefore, the selection data propagation holding register and the mode propagation holding register carry out none of unnecessary shifting operation in a bypass scan path selecting a register path at the time of propagation of test data and test result data. As a result, a time period can be reduced for shifting in test data and shifting out test result data.

Abstract: A logical synthesizing device and logical synthesizing method capable of generating a net list from a feedback loop added flip-flop excellent in layout efficiency. In a cell library, cells of feedback loop added flip-flop are newly registered together with existing various cells. The feedback loop portion of this feedback loop added flip-flop is formed in an optimum layout composition in consideration of the setup time and hold time. A logical synthesizing section, using the cells registered in the cell library, generates a net list for realizing a logical function description, and outputs to a test design section At this time, the feedback loop forming portion in the input and output of the flip-flop generates the net list by using the feedback loop added flip-flop.

Abstract: It is an object to obtain a semiconductor integrated circuit with reduced power consumption without reducing operation speed. In clock input control means (27), an exclusive OR gate (26a) receives comparison data (S1 and S2) and an NAND gate (27a) receives output of the exclusive OR gate (26a) and a reference clock (T) and outputs its output, a control signal (SC1) to an AND gate (G1) and an AND gate (G2) in a data holding portion (31a). An exclusive OR gate (26b) receives comparison data (S3 and S4) and an NAND gate (27b) receives the output of the exclusive OR gate (26b) and the reference clock (T), and outputs its output, a control signal (SC2) to an OR gate (G5) and an OR gate (G6) in a data holding portion (31b). Appropriately selecting the comparison data (S1-S4) allows data transfer at high speed of input data (D), output data (Q), inverted output data (QC), and so forth.

Abstract: A semiconductor integrated circuit device includes an internal function circuit formed on a first rectangular region on a rectangular semiconductor chip for implementing a function specific to the device, and a predetermined function control circuit formed on a second rectangular region for implementing a fixed function irrespective of the function implemented by said internal function circuit. First and second rectangular regions are separate regions. In the hierarchical design of an integrated circuit device, the circuit of the first rectangular region can be used as the structure component of another integrated circuit on another chip. The predetermined function control circuit can be laid out on the second rectangular region of another chip. The predetermined function control circuit is a testing circuit of boundary scan method, including a standardized structure component.

Abstract: Programmable logical blocks (3a to 3c) selected from a block library including information of a plurality of types of programmable logical blocks are disposed in a core region of a semiconductor integrated circuit (100). The degree of freedom of designing a field programmable gate array (FPGA) and the degree of integration are increased. A logic LSI is permitted to have redundancy to flexibly cope with design changes. This affords reduction in develop period and develop costs.

Abstract: A semiconductor integrated circuit, which can process n-bit (n is an integer, n>1) instructions or data at a time, has queues for storing instructions or data of m (m>1) times n bits received from an external memory through an instruction bus or a data bus. Therefore, it is possible to achieve an improvement in performance of the semiconductor integrated circuit and further to provide a low-priced semiconductor integrated circuit.

Abstract: A register circuit an arithmetic circuit a register circuit and a logic circuit form a bit slice cell corresponding to a path of propagation connecting the circuits in this order. Similarly, an arithmetic circuit register circuits and a logic circuit form a bit slice cell and an arithmetic circuit register circuits and a logic circuit form a bit slice cell. The bit slice cells are arranged generally in parallel to form a bit slice circuit which prevents redundant lines for connecting the functional circuits, whereby the bit slice circuit is developed in a short period without a decreased degree of integration and prolonged delay time.

Abstract: A bypass scan path is formed of a scan path and a scan path selecting circuit. The scan path has its operation controlled with a control signal group including a strobe signal, an update signal, shift clock signals. The scan path selecting circuit has its operation controlled with a reset signal and the control signal group for the scan path, and requires no other control signals. The reset signal and the control signal group for the scan path can be generated by a test controller defined in the standard of the boundary scan test of the IEEE 1149.1.

Abstract: In designing a layout of a semiconductor integrated circuit device having a large scale circuit block and logic circuit elements provided together, a power supply connecting line is formed rectilinearly to increase the integration density, reduce power supply noise and achieve automation of layout and interconnection. The semiconductor integrated circuit device includes one large scale circuit block and a plurality of logic circuit elements. VDD and GND annular power supply interconnecting lines are provided to surround the large scale circuit block. The annular power supply interconnecting lines extending in the lateral direction are divided into two lines to be disposed, respectively. Connection of the logic circuit elements and the annular power supply interconnecting lines are made by rectilinear VDD and GND power supply branch interconnecting lines.

Abstract: Test data applied serially from a data input terminal 6 is bypassed by a selecting circuit in modules that are not the object of testing and applied to a scan path in modules that are the object of testing. Test data is applied to the control point of the functional module from the scan path, and test result data provided from the observation point of the functional module and fetched by the scan path. The scan path shifts the fetched test result data to provide serially from a data output terminal 7. Each of selecting means 5a-5c operates in response to the selecting data held in the corresponding selecting data holding/propagating circuits 9a-9c. These selecting data holding/propagating circuits 9a-9c shift and hold selecting data applied serially from a data input terminal 10.

Abstract: A latch circuit comprises two inverters having their input terminals connected to their respective output terminals, i.e. cross-coupled to each other. In data writing, two data signals which are complementary to each other and applied from a circuit block at a preceding stage are respectively applied to the input terminals of these inverters. In data holding, the two complementary data signals applied in data writing are held at the connecting point of the inverters, and two complementary data signals to be applied to a circuit block at a succeeding stage are derived from the output terminals of the inverters. Therefore, when the data signals applied to the respective inverters are inverted in data writing, a change in the potential of the input terminal of one of the inverters accelerates a change in the output potential of the other inverter.

Abstract: Three shift path circuits (10', 20', 30') each comprising a bypass circuit are connected in series between a test data input (TDI) and a test data output (TDO). Each shift path circuit constitutes a design definition test data register connected to a circuit to be tested. Design modification of a testing circuit can be minimized by selectively operating the bypass circuit provided in a shift path circuit, even if there is circuit modification in the circuit to be tested. The period of time required for testing circuits to be tested is reduced.

Abstract: A data scan test circuit includes first through fourth latch circuits (L10 through L40). Data are latched in the third latch circuit (L40). A scan register consisting of the first, second and fourth latch circuits (L10, L20, L30) which become necessary when circuit blocks (CB1, CB2) are tested is made effective. Thus, unnecessary scan registers are put in the "through" state, thereby substantially reducing the number or scan paths in scan operation, and shortening the test time.

Abstract: A semiconductor apparatus including a semiconductor integrated circuit is disclosed. The semiconductor integrated circuit includes a circuit block, a plurality of boundary scan registers, a system data terminal, a test signal terminal and a control circuit. The control circuit responds to a test signal to generate control signals (a select signal LT, shift clock signals SCLK1 and SCLK2, a capture clock signal CPCLK and an update clock signal UPCLK) for controlling the boundary scan registers. The boundary scan registers are connected in cascade to each other and each connected to the circuit block. Each boundary scan register includes a selector circuit (12) and latch circuits (13, 14, 15). The latch circuit (13) responds to the shift clock signal SCLK1 to shift data of an adjacent preceding boundary scan register, an also responds to the update clock signal UPCLK to capture data from the selector circuit (12). The selector circuit (12) responds to the select signal LT to select system data or test data.

Abstract: In a circuit for testing integrated circuit devices, scan registers (8.about.16) and data selecting circuits (20-28) are connected between a plurality of circuit blocks (29.about.31) in correspondence with the number of bits of the data, with the scan registers connected to each other by a shift register path so as to have a function of one shift register as a whole. A register selecting circuit (20.about.28) is connected to a clock input terminal (T1, T2) of the scan register. The scan registers other than those corresponding to the logic circuit block to be tested are selected by the register selecting circuit. Consequently, clocks for scanning scan registers other than those provided before and after the required circuit block are eliminated, enabling reduction of time required for scan test.

Abstract: A programmable logic array comprises an OR circuit (67) and an AND circuit (68). A voltage lower than a power-supply voltage is applied to product term lines (57-60) from a power supply portion (69) in response to conduction of p channel transistors (31-34) by a clock signal to be precharged, and a voltage lower than the power-supply voltage is applied to output lines (54, 55) from a power supply portion (70) in response to conduction of p channel transistors (39, 40) by the clock signal. Therefore, applied voltages of the product term lines and the output lines are lowered, so that responsibility of circuit is improved, whereby a programmable logic array with a high speed operation is obtained.

Abstract: Oligo-imino-amines possessing plant-physiological activities and process for preparing the same are provided. Said substance is represented by the general formula. ##STR1## Wherein n=4-6.

Abstract: Compounds, which have antispasmodic effects, represented by the following formula (I) ##STR1## wherein R.sup.1 and R.sup.2, which may be the same or different, each represents a hydrogen atom, an alkoxy group or, when taken together, R.sup.1 and R.sup.2 represent an alkylenedioxy group; R.sup.3 represents a hydrogen atom, an alkyl group or a cycloalkyl group; R.sup.4, R.sup.5 and R.sup.6, which may be the same or different, each represents a hydrogen atom, an alkoxy group, an alkyl group, a halogen atom, a hydroxyl group or, when two of R.sup.4, R.sup.5 and R.sup.6 are taken together, they represent an alkylenedioxy group; and A represents a straight or branched chain alkylene group having 2 to 10 carbon atoms or an alkylene group having 2 to 10 carbon atoms and interrupted with an oxygen atom forming an ether bond therein, and the therapeutically useful acid-addition salts thereof; and a process for producing the same.