Patents by Inventor Takeshi Ichikawa

Takeshi Ichikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6339459
    Abstract: A liquid crystal display device comprises a matrix substrate in which a plurality of pixel electrodes are arrayed in a matrix pattern correspondence to colors of R (Red), G (Green), and B (Blue), an opposite substrate in which an opposite electrode is placed opposite to the pixel electrodes, and a liquid crystal material having negative dielectric anisotropy, the liquid crystal material being placed between the matrix substrate and the opposite substrate, wherein there are provided an alignment layer of polyimide with a vertical alignment property and a microlens array having a plurality of microlenses, the microlenses being provided at a pitch of two pixels relative to an array of the pixel electrodes.
    Type: Grant
    Filed: October 30, 1998
    Date of Patent: January 15, 2002
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takeshi Ichikawa, Katsumi Kurematsu, Osamu Koyama
  • Patent number: 6271897
    Abstract: A process of producing a semiconductor substrate for a liquid crystal display device which comprises: a display portion having a plurality of pixels and a thin film transistor comprising respective non-monocrystalline semiconductor active region connected to each said pixel; a peripheral circuit driving portion comprising a monocrystalline semiconductor region for receiving image input signals and driving said display portion, wherein said display portion and said peripheral circuit driving portion are monolithically formed; a first oxide film under said non-monocrystalline semiconductor region; and a second oxide film which is formed in said peripheral circuit driving portion and isolates an element constituting said peripheral circuit driving portion: which process is characterized in that first and second oxide film are formed in separate steps, and in that the second oxide film is formed thinner than the first oxide film.
    Type: Grant
    Filed: May 30, 1997
    Date of Patent: August 7, 2001
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takeshi Ichikawa, Akira Okita
  • Patent number: 6166792
    Abstract: A reflection type liquid crystal apparatus comprises a pixel electrode substrate carrying thereon a plurality of pixel electrodes, an opposite substrate disposed vis-a-vis said pixel electrodes and a liquid crystal material filling the gap between the substrates and adapted to display images by causing the pixel electrodes to reflect light entering from the opposite substrate. A reflection layer is arranged below a plurality of openings defined by the plurality of pixel electrodes to reflect light entering through the openings back to the openings.
    Type: Grant
    Filed: October 17, 1997
    Date of Patent: December 26, 2000
    Assignee: Canon Kabushiki Kaisha
    Inventors: Mamoru Miyawaki, Takeshi Ichikawa, Hiroo Akabori, Katsumi Kurematsu, Osamu Koyama
  • Patent number: 6163352
    Abstract: A liquid crystal apparatus comprises an active matrix substrate including a plurality of scanning lines and a plurality of signal lines, transistors arranged respectively at the crossings of the scanning lines and the signal lines and having the source region connected to the corresponding signal line and the gate region connected to the corresponding scanning line and pixel electrodes connected respectively to the drain regions of the transistors, an opposite substrate disposed oppositely relative to the active matrix substrate and a liquid crystal material filled in the space between the active matrix substrate and the opposite substrate. A source region is shared by each pair of adjacently located transistors and connected to the corresponding signal line.
    Type: Grant
    Filed: May 1, 2000
    Date of Patent: December 19, 2000
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takeshi Ichikawa, Mamoru Miyawaki, Katsumi Kurematsu, Osamu Koyama
  • Patent number: 6132800
    Abstract: Disclosed herein is a process for producing a color liquid crystal display device, which comprises the steps of forming a plurality of switching elements on a first transparent substrate; providing a coating layer on the plural switching elements; separately applying curable inks to predetermined opening areas between the switching elements by an ink-jet system to form a color filter; forming a transparent electrode on the color filter; forming a transparent electrode on a second transparent substrate; and charging a liquid crystal into a space between the first and second transparent substrates.
    Type: Grant
    Filed: February 21, 1997
    Date of Patent: October 17, 2000
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tetsuya Shimada, Shigetoshi Sugawa, Takeshi Miyazaki, Takeshi Ichikawa
  • Patent number: 6130851
    Abstract: An object of the present invention is to provide a semiconductor memory device capable of shortening the time required to complete all the tests without shifting a sample between processes for first and second probing tests. The semiconductor memory device according to the present invention comprises a redundant fuse provided between a source potential and a ground potential and composed of a material cut by the flow of a high current therethrough, a detector circuit which is electrically connected to a node provided on one electrode side of the redundant fuse and outputs a signal in response to a potential applied to the node, a selector circuit for selectively transferring input data to either of a normally-used memory cell and a redundant memory cell, a control circuit for controlling an electrical connection between the source potential and the redundant fuse, and voltage applying pads electrically connected to both ends of the redundant fuse.
    Type: Grant
    Filed: November 29, 1999
    Date of Patent: October 10, 2000
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Takeshi Ichikawa
  • Patent number: 6127998
    Abstract: A matrix substrate comprises a plurality of pixel electrodes arrayed in a matrix pattern, a plurality of switching elements connected to the pixel electrodes, a plurality of signal lines for supplying video signals to the plurality of switching elements, a plurality of scanning lines for supplying scanning signals to the plurality of switching elements, a horizontal driving circuit for supplying the video signals to the plurality of signal lines, and a vertical driving circuit for supplying the scanning signals to the plurality of scanning lines, wherein the horizontal driving circuit is comprised of a dynamic type circuit and the vertical driving circuit is comprised of a static type circuit.
    Type: Grant
    Filed: October 17, 1997
    Date of Patent: October 3, 2000
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takeshi Ichikawa, Mamoru Miyawaki, Katsumi Kurematsu, Osamu Koyama
  • Patent number: 6078368
    Abstract: A liquid crystal apparatus comprises an active matrix substrate including a plurality of scanning lines and a plurality of signal lines, transistors arranged respectively at the crossings of the scanning lines and the signal lines and having the source region connected to the corresponding signal line and the gate region connected to the corresponding scanning line and pixel electrodes connected respectively to the drain regions of the transistors, an opposite substrate disposed oppositely relative to the active matrix substrate and a liquid crystal material filled in the space between the active matrix substrate and the opposite substrate. A source region is shared by each pair of adjacently located transistors and connected to the corresponding signal line.
    Type: Grant
    Filed: July 12, 1999
    Date of Patent: June 20, 2000
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takeshi Ichikawa, Mamoru Miyawaki, Katsumi Kurematsu, Osamu Koyama
  • Patent number: 6078371
    Abstract: A microlens-equipped liquid crystal device capable of ensuring a high picture quality can be provided by obviating an adverse effect of a disclination of the liquid crystal at each pixel. Each microlens is disposed to form an optical axis deviated from the center of an associated pixel so as to form a condensed light spot substantially free from overlapping with a disclination (alignment disorder region) occurring along at least one side of a rectangular pixel.
    Type: Grant
    Filed: September 29, 1999
    Date of Patent: June 20, 2000
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takeshi Ichikawa, Katsumi Kurematsu, Osamu Koyama
  • Patent number: 6057557
    Abstract: A method of forming an Si film by a bias sputtering process comprises the steps of generating plasma between a target electrode holding a target material provided in a vacuum container and a substrate electrode holding a deposited film forming substrate, provided opposingly to the target electrode, by the use of a high-frequency energy to cause the target material to undergo sputtering, and applying a bias voltage to at least one of the target electrode and the substrate electrode to form an Si film comprised of atoms deposited by sputtering on the substrate, wherein;a mixed-gas environment comprising a mixture of an inert gas and a hydrogen gas is formed in the vacuum container, and the target material is subjected to sputtering while controlling H.sub.2 O gas, CO gas and CO.sub.2 gas in the mixed-gas environment to have a partial pressure of 1.0.times.10.sup.-8 Torr or less each, to form an epitaxial film on the substrate while maintaining a substrate temperature in the range of from 400.degree. C. to 700.
    Type: Grant
    Filed: July 8, 1999
    Date of Patent: May 2, 2000
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takeshi Ichikawa
  • Patent number: 6057897
    Abstract: A liquid crystal apparatus comprises an active matrix substrate including a plurality of scanning lines and a plurality of signal lines, transistors arranged respectively at the crossings of the scanning lines and the signal lines and having the source region connected to the corresponding signal line and the gate region connected to the corresponding scanning line and pixel electrodes connected respectively to the drain regions of the transistors, an opposite substrate disposed oppositely relative to the active matrix substrate and a liquid crystal material filled in the space between the active matrix substrate and the opposite substrate. A source region is shared by each pair of adjacently located transistors and connected to the corresponding signal line.
    Type: Grant
    Filed: October 17, 1997
    Date of Patent: May 2, 2000
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takeshi Ichikawa, Mamoru Miyawaki, Katsumi Kurematsu, Osamu Koyama
  • Patent number: 6049235
    Abstract: There are provided a semiconductor device, in which one electrode of each capacitor is connected to multiple input terminals and the other electrodes of the capacitors are commonly connected to a sense amplifier, and which has an analog signal processing circuit arranged between at least one of the multiple input terminals for inputting signals to the capacitors and the capacitors, and a unit for resetting the commonly connected electrode sides of the capacitors, a signal processing system having a plurality of semiconductor devices each identical to the semiconductor device and performing signal processing, and a calculation method using the semiconductor device, whereby arithmetic operations of analog signals can be easily attained and high-speed processing and low consumption power can be achieved with a small circuit scale.
    Type: Grant
    Filed: February 2, 1996
    Date of Patent: April 11, 2000
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takeshi Ichikawa, Mamoru Miyawaki
  • Patent number: 6034903
    Abstract: Disclosed is a semiconductor memory in which a repair device is easily positioned with respect to a redundancy fuse for a designation of replacement and a defect identification fuse. A semiconductor memory 1 includes sixteen blocks I/0300-I/0315 containing regular memory cells and redundancy memory cells, a fuse area 2 on one side, and sixteen I/O pads 3a-3p serving as connecting points, to the outside, of an internal circuit. The fuse area 2 includes a row redundancy fuse region 21, a column redundancy fuse region 22 and an operating fuse region 23. The operating fuse region 23 embraces operating fuses 231, 232 and an identification fuse 4 cut off when the internal circuit is defective, which are disposed adjacent to each other. An identification pad 5 for outputting a state of the identification fuse 4 to the outside is provided adjacent to the fuse area 2.
    Type: Grant
    Filed: September 4, 1998
    Date of Patent: March 7, 2000
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Takeshi Ichikawa
  • Patent number: 6022458
    Abstract: A method of forming a Si film by a bias sputtering process comprises the steps of generating plasma between a target electrode holding a target material provided in a vacuum container and a substrate electrode holding a deposited film forming substrate, provided opposingly to the target electrode, by the use of a high-frequency energy to cause the target material to undergo sputtering, and applying a bias voltage to at least one of the target electrode and the substrate electrode to form a Si film comprised of atoms deposited by sputtering on the substrate, wherein;a mixed-gas environment comprising a mixture of an inert gas and a hydrogen gas is formed in the vacuum container, and the target material is subjected to sputtering while controlling H.sub.2 O gas, CO gas and CO.sub.2 gas in the mixed-gas environment to have a partial pressure of 1.0.times.10.sup.-8 Torr or less each, to form an epitaxial film on the substrate while maintaining a substrate temperature in the range of from 400.degree. C. to 700.
    Type: Grant
    Filed: September 3, 1997
    Date of Patent: February 8, 2000
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takeshi Ichikawa
  • Patent number: 5994757
    Abstract: An electronic circuit device includes first and second conductors and a high-resistance member arranged therebetween. The high-resistance member consists of a material which changes from a high resistivity state to a low resistivity state in accordance with a voltage applied between the first and second conductors.
    Type: Grant
    Filed: February 3, 1995
    Date of Patent: November 30, 1999
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takeshi Ichikawa, Mamoru Miyawaki, Shunsuke Inoue
  • Patent number: 5978827
    Abstract: In a processor for performing operations including an addition of a plurality of multiple bit data, values on common places of a plurality of multiple bit data are entered in parallel into number detectors set for respective places, the number of the high signals in the input values is output in the binary notation, and outputs from a plurality of NDs are added by full adders to execute a high speed operation without carries. In addition, values with no common places are integrated into single data before being added.
    Type: Grant
    Filed: April 10, 1996
    Date of Patent: November 2, 1999
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takeshi Ichikawa
  • Patent number: 5918115
    Abstract: A semiconductor device including: an insulated gate type transistor having a columnar semiconductor region formed on the main side of a semiconductor substrate, a gate electrode formed on the side surface of the columnar semiconductor region while interposing a gate insulating film and main electrode regions respectively formed on and formed below the columnar semiconductor region; and a memory element which is formed on the upper main electrode region and which can be broken electrically.
    Type: Grant
    Filed: July 29, 1997
    Date of Patent: June 29, 1999
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shin Kikuchi, Mamoru Miyawaki, Genzo Monma, Hayao Ohzu, Shunsuke Inoue, Yoshio Nakamura, Takeshi Ichikawa, Osamu Ikeda, Tetsunobu Kohchi
  • Patent number: 5903043
    Abstract: In a semiconductor device, wherein capacitors are connected with multi-input terminals Q1 to Qn and one end of each capacitor is commonly connected to a sense amplifier, the semiconductor device comprises either the reset element for resetting the commonly connected capacitor terminals or the reset element which is connected between a capacitor and a switch, which is provided between a capacitor and an input terminal, and a structure in which inverted-phase-signals of the drive signals of the reset elements are input is connected with the same terminals as those of the reset elements, scaling down the circuit, improving the processing, and reducing the power consumption.
    Type: Grant
    Filed: October 26, 1995
    Date of Patent: May 11, 1999
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takeshi Ichikawa, Tetsunobu Kochi
  • Patent number: 5849163
    Abstract: A process for forming an epitaxial film on a biased substrate by sputtering a target to which a bias voltage and a plasma-generating high-frequency power are applied, wherein the film formation is carried out in an atmosphere having H.sub.2 O, CO and CO.sub.2 partial pressures controlled at 1.0.times.10.sup.-8 Torr, with the substrate temperature maintained in the range of from 400.degree. to 700.degree. C. The epitaxial film obtained by the process has excellent interface characteristics, very low impurity contents, good crystallinity and excellent step coverage, and is suitable for application to semiconductor devices.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: December 15, 1998
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takeshi Ichikawa, Hidemasa Mizutani
  • Patent number: 5693959
    Abstract: A thin film transistor comprises a source region, a drain region and a channel region formed in a thin film silicon region on an insulating substrate and a gate electrode formed via a gate insulating film on the channel region; at least one of the source region and the drain region has a high-concentration impurity region and a low-concentration impurity region; the channel region is in contact with the low-concentration impurity region; the low-concentration impurity region comprises at least a first region and a second region; the first region comprises a thin film having about the same thickness as the channel region; the second region comprises a thin film having about the same thickness as the high-concentration impurity region which is thicker than the first region. A liquid crystal display has TFT substrates wherein the thin film transistors are arranged in the form of a matrix.
    Type: Grant
    Filed: April 10, 1996
    Date of Patent: December 2, 1997
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shunsuke Inoue, Takeshi Ichikawa