Patents by Inventor Takeshi Matsumoto
Takeshi Matsumoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8824842Abstract: An optical semiconductor device, includes: a plurality of first diffraction grating layers disposed at a spacing from each other along first direction above first semiconductor layer, length of a lower surface of each of a plurality of first diffraction gratings along first direction being longer than a length of an upper surface of first diffraction grating; second diffraction grating layer disposed along first direction above first semiconductor layer, first and second diffraction grating layers being alternately disposed at a spacing from each other, a length of an upper surface of second diffraction grating layer along first direction being longer than the length of a lower surface of second diffraction layer; a diffraction grating including first and second diffraction grating layers; a second semiconductor layer disposed between first and second diffraction grating layers and under second diffraction grating layer; and third semiconductor layer disposed on first and second diffraction grating layers.Type: GrantFiled: March 8, 2011Date of Patent: September 2, 2014Assignee: Fujitsu LimitedInventor: Takeshi Matsumoto
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Publication number: 20140199492Abstract: An ion implanter that introduces a process gas into an ion source, extracts a ribbon-shaped ion beam from the ion source using an extraction electrode system made up of multiple electrodes, and uses the ion beam to irradiate a substrate disposed in a processing chamber during ion implantation processing, and that also introduces a cleaning gas into the ion source and performs cleaning inside said ion source at times other than during ion implantation processing, wherein during the re-initiation of the ion beam upon termination of cleaning, a predetermined voltage is applied to the extraction electrode system and the operating parameters of the ion source are then set to values corresponding to the implantation recipe of the substrate to be processed.Type: ApplicationFiled: October 25, 2013Publication date: July 17, 2014Applicant: NISSIN ION EQUIPMENT CO., LTD.Inventor: Takeshi MATSUMOTO
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Patent number: 8686564Abstract: A first transistor group, a second transistor group, and an electrode pad are formed on a semiconductor substrate. A first protective film is formed so as to cover the semiconductor substrate except for an upper region of the electrode pad. The second protective film which generates a stress in a projecting direction is formed so as to cover the first protective film except for an upper region of the first transistor group. A transistor ability of the first transistor group is varied to be relatively higher due to a presence of the second protective film, based on a transistor ability of the second transistor group, as a reference.Type: GrantFiled: February 24, 2012Date of Patent: April 1, 2014Assignee: Panasonic CorporationInventor: Takeshi Matsumoto
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Publication number: 20140036948Abstract: An optical semiconductor device includes a semiconductor substrate; a lower cladding layer formed over the semiconductor substrate; a quantum well active layer formed on the lower cladding layer; a diffraction grating layer formed over the quantum well active layer and having diffraction gratings formed in a surface thereof; and an upper cladding layer formed on the diffraction gratings of the diffraction grating layer. Further, a band gap in outer regions of the quantum well active layer that are adjacent to outer end surfaces of the optical semiconductor device is greater than the band gap in an inner region of the quantum well active layer that is located between the outer regions, and a thickness of one or more layers, which include the lower cladding layer and positioned between the semiconductor substrate and the quantum well active layer, is greater than or equal to 2.3 ?m.Type: ApplicationFiled: July 17, 2013Publication date: February 6, 2014Inventors: Akinori HAYAKAWA, Takeshi Matsumoto
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Patent number: 8604683Abstract: An ion source includes a plasma generation chamber, at least one filament disposed inside the plasma generation chamber, at least one electrode disposed so as to be opposed to the plasma generation chamber, and configured to extract out an ion beam from the plasma generation chamber, and a plurality of permanent magnets disposed outside the plasma generation chamber, and configured to form cusped magnetic fields inside the plasma generation chamber, and a deposition preventive plate disposed parallel with an inner surface of a wall of the plasma generation chamber. The deposition preventive plate has recesses which are formed at such positions as to be opposed to the respective permanent magnets with the wall of the plasma generation chamber interposed in between.Type: GrantFiled: March 9, 2012Date of Patent: December 10, 2013Assignee: Nissin Ion Equipment Co., Ltd.Inventors: Yutaka Inouchi, Takeshi Matsumoto, Masahiro Tanii, Katsuharu Imai
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Patent number: 8588952Abstract: A substrate processing system, which repeats a carrying cycle in which a substrate is carried sequentially in a carrying order indicated by module numbers assigned to the modules, respectively, from the module of a lower module number to that of a higher module number, and is capable of processing substrates at a high throughput even if some modules become unusable and, thereafter, become usable. A controller controls a carrier such that the carrier carries a substrate taken out from the module preceding a multimodule unit including a plurality of modules to the module nest in the carrying order to the module of the multimodule unit from which a substrate is carried out at time nearest to time when the substrate was carried out from the module preceding the multimodule.Type: GrantFiled: January 18, 2011Date of Patent: November 19, 2013Assignee: Tokyo Electron LimitedInventors: Kenichirou Matsuyama, Takeshi Matsumoto
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Patent number: 8560108Abstract: Even when a module constituting a multi-module becomes an unavailable module, transfer of substrates can be promptly performed, while restricting generation of inferior products. When a destination module of a multi-module becomes unavailable before a substrate is transferred to the destination module, a destination of the substrate is changed to a module to which a substrate subsequent to the substrate is to be loaded. Upon generation of an unavailable module, before the transfer unit accesses the module on an upstream end of the transfer cycle, the transfer cycle proceeds until a precedent substrate becomes ready to be unloaded from the changed destination module. Alternatively, upon generation of an unavailable module, when the transfer unit is located on an upstream side of the unavailable module in the transfer cycle, the transfer operation of the transfer unit is made standby until a precedent substrate becomes ready to be unloaded in the changed destination module.Type: GrantFiled: December 17, 2010Date of Patent: October 15, 2013Assignee: Tokyo Electron LimitedInventors: Kenichirou Matsuyama, Takeshi Matsumoto
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Patent number: 8525332Abstract: A semiconductor device includes a semiconductor substrate having a plurality of electrode pads, a protective film covering the upper surface of the semiconductor substrate and having an opening so that the electrode pad is exposed therethrough, a metal film formed on the electrode pad exposed through the opening, and a bump formed on the metal film. The metal film includes a plurality of grooves radially formed from the center thereof toward the periphery thereof.Type: GrantFiled: September 12, 2011Date of Patent: September 3, 2013Assignee: Panasonic CorporationInventor: Takeshi Matsumoto
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Patent number: 8402082Abstract: A maintenance information management method comprising steps of: by a terminal processing apparatus, transmitting, to a management apparatus via a network, maintenance work information about an analyzer on which maintenance work has been performed; storing, in a maintenance work information storage section of the management apparatus, the maintenance work information transmitted via the network; and transmitting, to the terminal processing apparatus via the network, the maintenance work information of the analyzer, which is stored in the maintenance work information storage section.Type: GrantFiled: March 10, 2009Date of Patent: March 19, 2013Assignee: Sysmex CorporationInventors: Tadayuki Yamaguchi, Takeshi Matsumoto
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Publication number: 20130027141Abstract: A crystal resonator comprises a first vibrating region provided on a crystal wafer, a second vibrating region provided on the crystal wafer, the second vibrating region having a different thickness and positive/negative orientation of the X-axis from those of the first vibrating region, and excitation electrodes which are provided respectively on the first vibrating region and the second vibrating region for causing the vibrating regions to vibrate independently. Frequencies that change by different amounts from each other relative to a temperature change can be retrieved from one vibrating region and the other vibrating region. Thus, based on an oscillating frequency of the vibrating region in which a clear frequency change occurs relative to the temperature, the oscillating frequency of the other vibrating region can be controlled. Thereby, increases in the complexity of the crystal oscillator can be suppressed.Type: ApplicationFiled: July 27, 2012Publication date: January 31, 2013Applicant: NIHON DEMPA KOGYO CO., LTD.Inventors: MITSUAKI KOYAMA, TOSHIHIKO KAGAMI, TAKESHI MATSUMOTO, TAKERU MUTOH, MANABU ISHIKAWA, SHINICHI SATO
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Patent number: 8306646Abstract: When a product substrate passes a reference module which is an n-th module ahead of an inspection module in a transfer path, an inspection reservation signal for performing an inspection to a lot to which the product substrate belongs is outputted to the inspection module. When the inspection module is in trouble, the output of an inspection reservation signal for a product substrate is forbidden, and the product substrates to be transferred to the inspection module are transferred to a module which is next to the inspection module in a transfer order. When the trouble of the inspection module has been resolved and a substrate for confirmation inspection is preferentially transferred to the inspection module, an inspection reservation signal for the substrate for confirmation inspection is outputted, the substrate for confirmation inspection is transferred to the inspection module, and the confirmation inspection for the inspection module is performed.Type: GrantFiled: April 21, 2009Date of Patent: November 6, 2012Assignee: Tokyo Electron LimitedInventors: Tomohiro Kaneko, Takeshi Matsumoto
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Publication number: 20120271444Abstract: A substrate processing apparatus can efficiently perform a trial operation in conditions close to those of an actual operation. In the substrate processing apparatus 1 for taking substrates W out of a transfer chamber (FOUPs 1 to 4), processing the substrates W in each of processing modules 2 and returning the processed substrates W to the transfer chamber, a mode selection unit 31 selects an operation check mode for performing an operation check of wafer transfer devices 15 and 17 or the processing modules 2. Further, a job setting unit 32 sets control jobs for the operation check and a process job as a recipe executed on the substrate W. A controller 3 determines whether or not a first control job and a second control job to be executed subsequently after the first control job are allowed to be executed in parallel.Type: ApplicationFiled: April 19, 2012Publication date: October 25, 2012Applicant: TOKYO ELECTRON LIMITEDInventor: Takeshi Matsumoto
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Patent number: 8281207Abstract: A transmitter communicates with a receiver and an error corrector corrects bit errors generated during data transmission. The transmitter has a scrambler unit that scrambles data so that a running disparity of 0 and 1 in the input data is substantially zero. A bit-string converting unit 15 that adds bit data for ensuring a maximum run length of a serial bit string of the scrambled data and converts control information to bit data of a fixed value. A synchronization timing generating unit 16 divides the transmitted data by a constant interval and converts the transmission data to a data block. A bit-string converting unit extracts a fixed-value bit pattern of the control data from the bit string of the data block, converts the bit pattern to the control information, and discriminates the data and the control information. A descrambler unit reconverts the data-scrambled data to the data before scrambling.Type: GrantFiled: November 17, 2006Date of Patent: October 2, 2012Assignee: Alaxala Networks CorporationInventors: Hidehiro Toyoda, Takayuki Muranaka, Takeshi Matsumoto, Naohisa Koie
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Publication number: 20120229012Abstract: An ion source includes a plasma generation chamber, at least one filament disposed inside the plasma generation chamber, at least one electrode disposed so as to be opposed to the plasma generation chamber, and configured to extract out an ion beam from the plasma generation chamber, and a plurality of permanent magnets disposed outside the plasma generation chamber, and configured to form cusped magnetic fields inside the plasma generation chamber, and a deposition preventive plate disposed parallel with an inner surface of a wall of the plasma generation chamber. The deposition preventive plate has recesses which are formed at such positions as to be opposed to the respective permanent magnets with the wall of the plasma generation chamber interposed in between.Type: ApplicationFiled: March 9, 2012Publication date: September 13, 2012Applicant: NISSIN ION EQUIPMENT CO., LTD.Inventors: Yutaka Inouchi, Takeshi Matsumoto, Masahiro Tanii, Katsuharu Imai
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Patent number: 8258043Abstract: A manufacturing method of a thin film semiconductor substrate includes implanting ions at a specified depth into a semiconductor substrate, forming a bubble layer in the semiconductor substrate by vaporizing the ions through heating, bonding an insulating substrate onto the semiconductor substrate, and cleaving the semiconductor substrate along the bubble layer to form a semiconductor thin film on a side of the insulating substrate. At the forming, the semiconductor substrate is heated at a temperature in a temperature range of approximately 1000° C. to 1200° C. for a duration in a range of approximately 10 ?s to 100 ms. The heating of the semiconductor substrate is performed by using, for example, a light beam.Type: GrantFiled: September 2, 2011Date of Patent: September 4, 2012Assignees: National University Corporation Tokyo University of Agriculture and Technology, Nissin Ion Equipment Co., Ltd.Inventors: Toshiyuki Sameshima, Yutaka Inouchi, Takeshi Matsumoto, Yuko Fujimoto
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Patent number: 8243261Abstract: An optical property measurement apparatus includes: a main body which includes a plane-shape surface that is so disposed as to face the display portion; an optical sensor which receives light directed from an opening that is formed through the plane-shape surface; and a support portion which is disposed on a side of the plane-shape surface and keeps a constant distance between the display portion and the plane-shape surface; wherein a light shield portion that is so disposed as to enclose a circumferential area of the opening of the plane-shape surface and shields entrance of light from a region other than a measurement target region of the display portion when the optical property is measured.Type: GrantFiled: October 7, 2009Date of Patent: August 14, 2012Assignee: Konica Minolta Sensing, Inc.Inventors: Takeshi Matsumoto, Shinji Yamamoto, Kenji Imura, Kazuya Kiyoi, Yoshiyuki Nagashima, Yasushi Goto
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Publication number: 20120153491Abstract: A first transistor group, a second transistor group, and an electrode pad are formed on a semiconductor substrate. A first protective film is formed so as to cover the semiconductor substrate except for an upper region of the electrode pad. The second protective film which generates a stress in a projecting direction is formed so as to cover the first protective film except for an upper region of the first transistor group. A transistor ability of the first transistor group is varied to be relatively higher due to a presence of the second protective film, based on a transistor ability of the second transistor group, as a reference.Type: ApplicationFiled: February 24, 2012Publication date: June 21, 2012Applicant: PANASONIC CORPORATIONInventor: TAKESHI MATSUMOTO
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Publication number: 20120077331Abstract: A manufacturing method of a thin film semiconductor substrate includes implanting ions at a specified depth into a semiconductor substrate, forming a bubble layer in the semiconductor substrate by vaporizing the ions through heating, bonding an insulating substrate onto the semiconductor substrate, and cleaving the semiconductor substrate along the bubble layer to form a semiconductor thin film on a side of the insulating substrate. At the forming, the semiconductor substrate is heated at a temperature in a temperature range of approximately 1000° C. to 1200° C. for a duration in a range of approximately 10 ?s to 100 ms. The heating of the semiconductor substrate is performed by using, for example, a light beam.Type: ApplicationFiled: September 2, 2011Publication date: March 29, 2012Applicants: NISSIN ION EQUIPMENT CO., LTD., National University Corporation Tokyo University of Agriculture and TechnologyInventors: Toshiyuki SAMESHIMA, Yutaka Inouchi, Takeshi Matsumoto, Yuko Fujimoto
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Publication number: 20110317729Abstract: A current driving device comprises; a three-terminal regulator configuration circuit operative as a three-terminal regulator which drops a voltage of a first electric power supply to a predetermined target output voltage in a state where a main terminal and a control terminal of a power transistor are connected to a main terminal connection terminal and a control terminal connection terminal, respectively; a voltage setting circuit which sets a control voltage corresponding to a target output voltage which is applied from the three-terminal regulator configuration circuit to the control terminal of the power transistor; and a voltage restricting circuit which is connected to the control terminal connection terminal and controls the control voltage applied to the control terminal of the power transistor so that the output voltage of the three-terminal regulator configuration circuit becomes a predetermined voltage or less, upon being supplied with the electric power from the first electric power supply.Type: ApplicationFiled: June 23, 2011Publication date: December 29, 2011Inventors: Takeshi MATSUMOTO, Kenichi Tatehara, Toshiyuki Shimada, Yuichi Takahashi
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Publication number: 20110316154Abstract: A semiconductor device includes a semiconductor substrate having a plurality of electrode pads, a protective film covering the upper surface of the semiconductor substrate and having an opening so that the electrode pad is exposed therethrough, a metal film formed on the electrode pad exposed through the opening, and a bump formed on the metal film. The metal film includes a plurality of grooves radially formed from the center thereof toward the periphery thereof.Type: ApplicationFiled: September 12, 2011Publication date: December 29, 2011Applicant: Panasonic CorporationInventor: Takeshi MATSUMOTO