Abstract: A first lens group unit 20 includes a lens L2, a blacked-out portion L2b, a lens frame 22, and an injection hole 21a. The lens L2 has a thrust surface L2d that intersects the direction of the optical axis AX, a thrust surface L2c on the opposite side from the thrust surface L2d, and an edge surface L2e that connects the thrust surface L2d and the thrust surface L2c. The blacked-out portion L2b is provided to an edge surface L2e of the lens L2, and suppresses the reflection of light incident on the lens L2 on the edge surface L2e. The lens frame 22 has a substantially cylindrical shape, and holds the lens L2, which is inserted from the thrust surface L2d side along the cylindrical inner peripheral surface 22a. The injection hole 21a is used to bond the lens L2 and the lens frame 22 with an adhesive applied to the thrust surface L2c.

Abstract: An ultrasonic wave generation device including: an ultrasonic wave generation source; an ultrasonic wave condensation part; and a waveguide. The ultrasonic wave condensation part has a first reflection surface opposed to the ultrasonic wave generation source and a second reflection surface opposed to the first reflection surface. The first reflection surface reflects the ultrasonic wave, generated from the ultrasonic wave generation source, toward the second reflection surface. The second reflection surface reflects the ultrasonic wave, which has been reflected by the first reflection surface, toward the waveguide so as to introduce the ultrasonic wave into the waveguide. The waveguide protrudes from the first reflection surface to a side opposite the second reflection surface. A recessed portion is formed from the first reflection surface to the second reflection surface side along an outer circumferential surface of the waveguide.

Abstract: An ultrasonic generator includes an ultrasonic wave source and a converging portion. The converging portion includes a first reflecting portion which reflects the ultrasonic wave generated by the ultrasonic wave source on its first reflecting surface, a second reflecting portion which reflects the ultrasonic wave reflected by the first reflecting surface on its second reflecting surface, and a waveguide serving as a transmission path for the ultrasonic wave. The waveguide is disposed such that the ultrasonic wave reflected by the second reflecting surface is introduced through an introduction portion thereof. The focal point of the second reflecting surface and the focal point of the first reflecting surface are disposed such that the ultrasonic wave reflected by the second reflecting surface becomes a plane wave.

Abstract: A display device includes: a light emitting panel having a light emitting surface; a cover panel configured to cover the light emitting surface; and a cooling unit that is arranged in a space between the cover panel and the light emitting panel and configured to cool the light emitting panel. The cooling unit includes a frame portion that surrounds an outer periphery of the space, and a coolant configured to be supplied into the space from outside of the space and discharged from the space to the outside of the space.

Abstract: An ultrasonic generator includes an ultrasonic wave source and a converging portion. The converging portion includes a first reflecting portion which reflects the ultrasonic wave generated by the ultrasonic wave source on its first reflecting surface, a second reflecting portion which reflects the ultrasonic wave reflected by the first reflecting surface on its second reflecting surface, and a waveguide serving as a transmission path for the ultrasonic wave. The waveguide is disposed such that the ultrasonic wave reflected by the second reflecting surface is introduced through an introduction portion thereof. The focal point of the second reflecting surface and the focal point of the first reflecting surface are disposed such that the ultrasonic wave reflected by the second reflecting surface becomes a plane wave.

Abstract: In a semiconductor device that uses an N-channel MOS transistor as an electrostatic protection element, the N-channel MOS transistor has a plurality of electric field relaxing areas, three of which have in a longitudinal direction three different impurity concentrations decreasing from an N-type high concentration drain region downward, and three of which have in a lateral direction three different impurity concentrations decreasing from the N-type high concentration drain region toward a channel region. An electric field relaxing area that is in contact with the electric field relaxing areas in the longitudinal direction and with the electric field relaxing areas in the lateral direction has the lowest impurity concentration.

Abstract: A semiconductor device (10) includes: a substrate (1); a wiring (6) formed above the substrate (1); a titanium nitride film (7) formed on the wiring (6); an oxide film (3) formed on the titanium nitride film (7); a silicon nitride film (4) formed on the oxide film (3); and a pad portion (8) exposing the wiring (6), and formed at a place where a first opening portion (91) formed in the silicon nitride film (4) and a second opening portion (92) formed in the titanium nitride film (7) overlap with each other in plan view, and being inside a third opening portion (93) formed in the oxide film (3) in plan view, wherein the silicon nitride film (4) is formed on top of and in contact with the titanium nitride film (7) inside the third opening portion (93) in plan view.

Abstract: A semiconductor device (10) includes: a substrate (1); a wiring (6) formed above the substrate (1); a titanium nitride film (7) formed on the wiring (6); an oxide film (3) formed on the titanium nitride film (7); a silicon nitride film (4) formed on the oxide film (3); and a pad portion (8) exposing the wiring (6), and formed at a place where a first opening portion (91) formed in the silicon nitride film (4) and a second opening portion (92) formed in the titanium nitride film (7) overlap with each other in plan view, and being inside a third opening portion (93) formed in the oxide film (3) in plan view, wherein the silicon nitride film (4) is formed on top of and in contact with the titanium nitride film (7) inside the third opening portion (93) in plan view.

Abstract: A semiconductor device includes: a substrate; a wiring formed above the substrate; a titanium nitride film formed on the wiring; an oxide film formed on the titanium nitride film; a silicon nitride film formed on the oxide film; and a pad portion exposing the wiring, and formed at a place where a first opening portion formed in the silicon nitride film and a second opening portion formed in the titanium nitride film overlap with each other in plan view, and being inside a third opening portion formed in the oxide film in plan view, wherein the silicon nitride film is formed on top of and in contact with the titanium nitride film inside the third opening portion in plan view.

Abstract: In a semiconductor device that uses an N-channel MOS transistor as an electrostatic protection element, the N-channel MOS transistor has a plurality of electric field relaxing areas, three of which have in a longitudinal direction three different impurity concentrations decreasing from an N-type high concentration drain region downward, and three of which have in a lateral direction three different impurity concentrations decreasing from the N-type high concentration drain region toward a channel region. An electric field relaxing area that is in contact with the electric field relaxing areas in the longitudinal direction and with the electric field relaxing areas in the lateral direction has the lowest impurity concentration.

Abstract: According to one embodiment, an apparatus for manufacturing a display device, includes: a first holding section configured to hold a first substrate; a second holding section configured to hold a second substrate; a turning section configured to turn the first holding section such that the first substrate and the second substrate face each other; a support section configured to support the first holding section after the turning; an adjustment section; and an elevation section. The adjustment section is provided at an upper end of the support section and is configured to adjust a distance between the first holding section after the turning and the upper end of the support section. The elevation section is configured to elevate the second holding section and attach the first substrate and the second substrate via an adhesive layer.

Abstract: An input shaft (1) connectable to an engine (5), an output gear (2), a transmission case (3) and a Ravigneaux planetary gear unit (4) are provided. Four rotational elements of the Ravigneaux planetary gear unit (4) are a single pinion side sun gear (Ss), a carrier (C), a ring gear (R) and a double pinion side sun gear (Sd) which are arranged orderly on a common speed diagram. The single pinion side sun gear (Ss) is constantly connected to a motor/generator (6), and the ring gear (R) is constantly connected to the output gear (2). And, with usage of a low & reverse clutch (L&R/C), a high clutch (H/C) and a low brake (L/B), a first speed (1st), a second speed (2nd), a third speed (3rd) and a stepless change speed (eCVT) are established.

Abstract: In a semiconductor device that uses an N-channel MOS transistor as an electrostatic protection element, the N-channel MOS transistor has a plurality of electric field relaxing areas, three of which have in a longitudinal direction three different impurity concentrations decreasing from an N-type high concentration drain region downward, and three of which have in a lateral direction three different impurity concentrations decreasing from the N-type high concentration drain region toward a channel region. An electric field relaxing area that is in contact with the electric field relaxing areas in the longitudinal direction and with the electric field relaxing areas in the lateral direction has the lowest impurity concentration.

Abstract: A semiconductor device includes: a substrate; a wiring formed above the substrate; a titanium nitride film formed on the wiring; an oxide film formed on the titanium nitride film; a silicon nitride film formed on the oxide film; and a pad portion exposing the wiring, and formed at a place where a first opening portion formed in the silicon nitride film and a second opening portion formed in the titanium nitride film overlap with each other in plan view, and being inside a third opening portion formed in the oxide film in plan view, wherein the silicon nitride film is formed on top of and in contact with the titanium nitride film inside the third opening portion in plan view.

Abstract: The present disclosure provides compositions and methods for treating pruritis and for treating certain types of pain.

Abstract: In a semiconductor device that uses an N-channel MOS transistor as an electrostatic protection element, the N-channel MOS transistor has a plurality of electric field relaxing areas, three of which have in a longitudinal direction three different impurity concentrations decreasing from an N-type high concentration drain region downward, and three of which have in a lateral direction three different impurity concentrations decreasing from the N-type high concentration drain region toward a channel region. An electric field relaxing area that is in contact with the electric field relaxing areas in the longitudinal direction and with the electric field relaxing areas in the lateral direction has the lowest impurity concentration.

Abstract: Provided is a semiconductor device including a second conductivity type low-concentration diffusion layer (101) for an electric field relaxation reaching a lower portion of a gate oxide film so as to cover a drain diffusion layer (107), in which a second conductivity type medium-concentration diffusion layer (102) is formed within the second conductivity type low-concentration diffusion layer (101) for the electric field relaxation, and a second conductivity type high-concentration diffusion layer (103), which has a high concentration and small variation in structure due to suppression of heat treatment as much as possible, is formed within the second conductivity type medium-concentration diffusion layer (102).

Abstract: In a tape recording medium, a sliding layer has an electric resistance of 1×108 ?/sq or less, and contains carbon particles and solid particles. The carbon particles have a primary particle size of 30 nm or less and a BET specific surface area of 100 m2/g or more. The solid particles have a primary particle size of 100 nm or less, a Mohs' hardness in a range from 2.5 to 8, inclusive, a density of 3 g/cm3 or more, and a BET specific surface area of 30 m2/g or more.

Abstract: A semiconductor device includes a semiconductor substrate, and a multi-level interconnection structure that is provided on the semiconductor substrate and that has a plurality of interconnection layers stacked one on another. Each interconnection layer includes a real interconnection and a dummy interconnection covered with an insulative film. The interconnection layers include a first interconnection layer including a first real interconnection, a second interconnection layer stacked on the first interconnection layer and including an overlapping dummy interconnection that overlaps the first real interconnection in a stacking direction of the plurality of interconnection layers in a sectional view, and a third interconnection layer stacked on the second interconnection layer and including a second real interconnection that overlaps the overlapping dummy interconnection in the stacking direction of the plurality of interconnection layers in the sectional view.

Abstract: According to one embodiment, an apparatus for manufacturing a display device, includes: a first holding section configured to hold a first substrate; a second holding section configured to hold a second substrate; a turning section configured to turn the first holding section such that the first substrate and the second substrate face each other; an elevation unit configured to elevate the second holding section and attach the first substrate and the second substrate via an adhesive layer; and a first radiation section configured to radiate ultraviolet rays from at least one direction of an inclined lower side of an opening of a space between the first substrate and the second substrate and an inclined upper side of the opening toward the opening.