Patents by Inventor Takeshi Morita

Takeshi Morita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11185594
    Abstract: As an antitumor drug which is excellent in terms of antitumor effect and safety and has an excellent therapeutic effect, there is provided an antibody-drug conjugate in which an antitumor compound represented by the following formula is conjugated to an anti-HER2 antibody via a linker having a structure represented by the formula: L1-L2-LP-NH—(CH2)n1-La-Lb-Lc or -L1-L2-LP- wherein the anti-HER2 antibody is connected to the terminal L1, and the antitumor compound is connected to the terminal Lc or LP with the nitrogen atom of the amino group at position 1 as the connecting position.
    Type: Grant
    Filed: April 6, 2015
    Date of Patent: November 30, 2021
    Assignee: DAIICHI SANKYO COMPANY, LIMITED
    Inventors: Hiroyuki Naito, Takeshi Masuda, Takashi Nakada, Masao Yoshida, Shinji Ashida, Hideki Miyazaki, Yuji Kasuya, Koji Morita, Yusuke Ogitani, Yuki Abe
  • Patent number: 11180688
    Abstract: Provided are: a spherical magnesium oxide having not only high sphericity but also smooth surface and having excellent moisture resistance and excellent filling properties, and a method producing the same. In the present invention, by controlling the boron and iron contents of the calcined magnesium oxide to be in the respective predetermined ranges, there is provided a spherical magnesium oxide having a volume-based cumulative 50% particle diameter (D50), as measured by a laser diffraction/scattering particle size distribution measurement, in the range of from 3 to 200 ?m, which is the range for a relatively large particle diameter, and a high sphericity of 1.00 to 1.20, as measured from viewing a SEM photomicrograph, as well as smooth surface, and having excellent moisture resistance and excellent filling properties. A predetermined spherical magnesium oxide is provided by virtue of the synergies obtained from the boron content of 300 to 2,000 ppm and the iron content of 100 to 1,500 ppm.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: November 23, 2021
    Assignee: TATEHO CHEMICAL INDUSTRIES CO., LTD.
    Inventors: Takeshi Konishi, Mareshi Takegaki, Yoshihisa Osaki, Tomoaki Chikazawa, Akinori Saito, Yuki Morita
  • Patent number: 11153700
    Abstract: A signal delay adjustment device for individually setting delay times of audio signals supplied to a plurality of speakers and individually delaying the audio signals supplied to the plurality of speakers with set delay times to adjust output timings of sounds among the plurality of speakers is configured to include a setting part to set a delay time applied to the audio signal for each speaker, and a delay part for individually delaying the audio signal to be supplied to the plurality of speakers based on the delay time set by the setting part. The delay part gradually changes the delay time to be applied to the audio signal over a predetermined time so that the delay time to be applied to the audio signal reaches the delay time set by the setting part over the predetermined time.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: October 19, 2021
    Assignee: CLARION CO., LTD.
    Inventors: Hideyuki Morita, Takeshi Hashimoto
  • Patent number: 11146695
    Abstract: A communication management system, a communication system, a communication control method, and a recording medium.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: October 12, 2021
    Assignee: RICOH COMPANY, LTD.
    Inventors: Takeshi Homma, Shigeru Nakamura, Yuichi Kawasaki, Hiroshi Hinohara, Kenichiro Morita, Atsushi Miyamoto
  • Publication number: 20210299554
    Abstract: Disclosed herein is an input device including: a plurality of input members; an upper surface having a right region in which a part of the plurality of input members is disposed, a left region in which another part of the plurality of input members is disposed, and a center region that is a region between the right region and the left region; and a light emitting region formed along an outer edge of the center region. The light emitting region includes a first light emitting portion configured to indicate identification information assigned to a plurality of input devices connected to an information processing apparatus, and a second light emitting portion configured to emit light based on information different from the identification information.
    Type: Application
    Filed: March 17, 2021
    Publication date: September 30, 2021
    Applicant: Sony Interactive Entertainment Inc.
    Inventors: Ikuo KOBAYASHI, Takeshi IGARASHI, Masaho MORITA, Kazuyuki SUZUKI, Akinori ITO
  • Publication number: 20210299552
    Abstract: Disclosed herein is an input device including a first microphone, an exterior member that accommodates the first microphone, and a first sound hole penetrating the exterior member to be connected to the first microphone. An exterior surface of the exterior member has one or a plurality of wall portions that surround the first sound hole.
    Type: Application
    Filed: March 22, 2021
    Publication date: September 30, 2021
    Applicant: Sony Interactive Entertainment Inc.
    Inventors: Masaho MORITA, Takeshi IGARASHI
  • Publication number: 20210249623
    Abstract: A display device includes: a light emitting panel having a light emitting surface; a cover panel configured to cover the light emitting surface; and a cooling unit that is arranged in a space between the cover panel and the light emitting panel and configured to cool the light emitting panel. The cooling unit includes a frame portion that surrounds an outer periphery of the space, and a coolant configured to be supplied into the space from outside of the space and discharged from the space to the outside of the space.
    Type: Application
    Filed: January 14, 2021
    Publication date: August 12, 2021
    Applicant: DENSO TEN Limited
    Inventors: Atsushi YAMAWAKI, Takeshi MORITA
  • Publication number: 20210169450
    Abstract: An ultrasonic generator includes an ultrasonic wave source and a converging portion. The converging portion includes a first reflecting portion which reflects the ultrasonic wave generated by the ultrasonic wave source on its first reflecting surface, a second reflecting portion which reflects the ultrasonic wave reflected by the first reflecting surface on its second reflecting surface, and a waveguide serving as a transmission path for the ultrasonic wave. The waveguide is disposed such that the ultrasonic wave reflected by the second reflecting surface is introduced through an introduction portion thereof. The focal point of the second reflecting surface and the focal point of the first reflecting surface are disposed such that the ultrasonic wave reflected by the second reflecting surface becomes a plane wave.
    Type: Application
    Filed: December 1, 2020
    Publication date: June 10, 2021
    Applicant: NGK SPARK PLUG CO., LTD.
    Inventors: Takeshi MORITA, Kang CHEN, Takashi IIJIMA, Takasuke IRIE
  • Patent number: 10777544
    Abstract: In a semiconductor device that uses an N-channel MOS transistor as an electrostatic protection element, the N-channel MOS transistor has a plurality of electric field relaxing areas, three of which have in a longitudinal direction three different impurity concentrations decreasing from an N-type high concentration drain region downward, and three of which have in a lateral direction three different impurity concentrations decreasing from the N-type high concentration drain region toward a channel region. An electric field relaxing area that is in contact with the electric field relaxing areas in the longitudinal direction and with the electric field relaxing areas in the lateral direction has the lowest impurity concentration.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: September 15, 2020
    Assignee: ABLIC INC.
    Inventors: Takeshi Morita, Kazuhiro Tsumura
  • Patent number: 10388618
    Abstract: A semiconductor device (10) includes: a substrate (1); a wiring (6) formed above the substrate (1); a titanium nitride film (7) formed on the wiring (6); an oxide film (3) formed on the titanium nitride film (7); a silicon nitride film (4) formed on the oxide film (3); and a pad portion (8) exposing the wiring (6), and formed at a place where a first opening portion (91) formed in the silicon nitride film (4) and a second opening portion (92) formed in the titanium nitride film (7) overlap with each other in plan view, and being inside a third opening portion (93) formed in the oxide film (3) in plan view, wherein the silicon nitride film (4) is formed on top of and in contact with the titanium nitride film (7) inside the third opening portion (93) in plan view.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: August 20, 2019
    Assignee: ABLIC Inc.
    Inventors: Takeshi Morita, Shinjiro Kato, Masaru Akino, Yukihiro Imura
  • Publication number: 20190189575
    Abstract: A semiconductor device (10) includes: a substrate (1); a wiring (6) formed above the substrate (1); a titanium nitride film (7) formed on the wiring (6); an oxide film (3) formed on the titanium nitride film (7); a silicon nitride film (4) formed on the oxide film (3); and a pad portion (8) exposing the wiring (6), and formed at a place where a first opening portion (91) formed in the silicon nitride film (4) and a second opening portion (92) formed in the titanium nitride film (7) overlap with each other in plan view, and being inside a third opening portion (93) formed in the oxide film (3) in plan view, wherein the silicon nitride film (4) is formed on top of and in contact with the titanium nitride film (7) inside the third opening portion (93) in plan view.
    Type: Application
    Filed: February 11, 2019
    Publication date: June 20, 2019
    Inventors: Takeshi MORITA, Shinjiro Kato, Masaru Akino, Yukihiro Imura
  • Patent number: 10249584
    Abstract: A semiconductor device includes: a substrate; a wiring formed above the substrate; a titanium nitride film formed on the wiring; an oxide film formed on the titanium nitride film; a silicon nitride film formed on the oxide film; and a pad portion exposing the wiring, and formed at a place where a first opening portion formed in the silicon nitride film and a second opening portion formed in the titanium nitride film overlap with each other in plan view, and being inside a third opening portion formed in the oxide film in plan view, wherein the silicon nitride film is formed on top of and in contact with the titanium nitride film inside the third opening portion in plan view.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: April 2, 2019
    Assignee: ABLIC INC.
    Inventors: Takeshi Morita, Shinjiro Kato, Masaru Akino, Yukihiro Imura
  • Publication number: 20190006347
    Abstract: In a semiconductor device that uses an N-channel MOS transistor as an electrostatic protection element, the N-channel MOS transistor has a plurality of electric field relaxing areas, three of which have in a longitudinal direction three different impurity concentrations decreasing from an N-type high concentration drain region downward, and three of which have in a lateral direction three different impurity concentrations decreasing from the N-type high concentration drain region toward a channel region. An electric field relaxing area that is in contact with the electric field relaxing areas in the longitudinal direction and with the electric field relaxing areas in the lateral direction has the lowest impurity concentration.
    Type: Application
    Filed: September 6, 2018
    Publication date: January 3, 2019
    Inventors: Takeshi MORITA, Kazuhiro TSUMURA
  • Patent number: 10120216
    Abstract: According to one embodiment, an apparatus for manufacturing a display device, includes: a first holding section configured to hold a first substrate; a second holding section configured to hold a second substrate; a turning section configured to turn the first holding section such that the first substrate and the second substrate face each other; a support section configured to support the first holding section after the turning; an adjustment section; and an elevation section. The adjustment section is provided at an upper end of the support section and is configured to adjust a distance between the first holding section after the turning and the upper end of the support section. The elevation section is configured to elevate the second holding section and attach the first substrate and the second substrate via an adhesive layer.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: November 6, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takahide Miyahara, Takeshi Morita, Kentaro Miyazaki
  • Patent number: 10118478
    Abstract: An input shaft (1) connectable to an engine (5), an output gear (2), a transmission case (3) and a Ravigneaux planetary gear unit (4) are provided. Four rotational elements of the Ravigneaux planetary gear unit (4) are a single pinion side sun gear (Ss), a carrier (C), a ring gear (R) and a double pinion side sun gear (Sd) which are arranged orderly on a common speed diagram. The single pinion side sun gear (Ss) is constantly connected to a motor/generator (6), and the ring gear (R) is constantly connected to the output gear (2). And, with usage of a low & reverse clutch (L&R/C), a high clutch (H/C) and a low brake (L/B), a first speed (1st), a second speed (2nd), a third speed (3rd) and a stepless change speed (eCVT) are established.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: November 6, 2018
    Assignee: JATCO Ltd
    Inventors: Kenichi Watanabe, Takeshi Morita
  • Patent number: 10096591
    Abstract: In a semiconductor device that uses an N-channel MOS transistor as an electrostatic protection element, the N-channel MOS transistor has a plurality of electric field relaxing areas, three of which have in a longitudinal direction three different impurity concentrations decreasing from an N-type high concentration drain region downward, and three of which have in a lateral direction three different impurity concentrations decreasing from the N-type high concentration drain region toward a channel region. An electric field relaxing area that is in contact with the electric field relaxing areas in the longitudinal direction and with the electric field relaxing areas in the lateral direction has the lowest impurity concentration.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: October 9, 2018
    Assignee: ABLIC INC.
    Inventors: Takeshi Morita, Kazuhiro Tsumura
  • Publication number: 20180269169
    Abstract: A semiconductor device includes: a substrate; a wiring formed above the substrate; a titanium nitride film formed on the wiring; an oxide film formed on the titanium nitride film; a silicon nitride film formed on the oxide film; and a pad portion exposing the wiring, and formed at a place where a first opening portion formed in the silicon nitride film and a second opening portion formed in the titanium nitride film overlap with each other in plan view, and being inside a third opening portion formed in the oxide film in plan view, wherein the silicon nitride film is formed on top of and in contact with the titanium nitride film inside the third opening portion in plan view.
    Type: Application
    Filed: March 8, 2018
    Publication date: September 20, 2018
    Inventors: Takeshi MORITA, Shinjiro KATO, Masaru AKINO, Yukihiro IMURA
  • Publication number: 20180110757
    Abstract: The present disclosure provides compositions and methods for treating pruritis and for treating certain types of pain.
    Type: Application
    Filed: October 19, 2017
    Publication date: April 26, 2018
    Inventors: Diana M. Bautista, Takeshi Morita, Rose Zabel Hill, Rachel B. Brem
  • Publication number: 20170287898
    Abstract: In a semiconductor device that uses an N-channel MOS transistor as an electrostatic protection element, the N-channel MOS transistor has a plurality of electric field relaxing areas, three of which have in a longitudinal direction three different impurity concentrations decreasing from an N-type high concentration drain region downward, and three of which have in a lateral direction three different impurity concentrations decreasing from the N-type high concentration drain region toward a channel region. An electric field relaxing area that is in contact with the electric field relaxing areas in the longitudinal direction and with the electric field relaxing areas in the lateral direction has the lowest impurity concentration.
    Type: Application
    Filed: March 27, 2017
    Publication date: October 5, 2017
    Inventors: Takeshi MORITA, Kazuhiro TSUMURA
  • Publication number: 20170271453
    Abstract: Provided is a semiconductor device including a second conductivity type low-concentration diffusion layer (101) for an electric field relaxation reaching a lower portion of a gate oxide film so as to cover a drain diffusion layer (107), in which a second conductivity type medium-concentration diffusion layer (102) is formed within the second conductivity type low-concentration diffusion layer (101) for the electric field relaxation, and a second conductivity type high-concentration diffusion layer (103), which has a high concentration and small variation in structure due to suppression of heat treatment as much as possible, is formed within the second conductivity type medium-concentration diffusion layer (102).
    Type: Application
    Filed: March 15, 2017
    Publication date: September 21, 2017
    Inventors: Keisuke NAGAO, Takeshi MORITA