Patents by Inventor Takeshi Sakai

Takeshi Sakai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250113546
    Abstract: A semiconductor device includes a gate electrode, an oxide semiconductor layer having a polycrystalline structure, and a gate insulating layer between the gate electrode and the oxide semiconductor layer. The oxide semiconductor layer includes a source region and a drain region each containing an impurity element, a channel region between the source region and the drain region, and a first region adjacent to the channel region. The first region includes a first edge extending along a first direction travelling from the source region to the drain region. The first region has a higher electrical resistivity than each of the source region and the drain region. An etching rate of the oxide semiconductor layer is less than 3 nm/min when the oxide semiconductor layer is etched using an etching solution containing phosphoric acid as a main component at 40° C.
    Type: Application
    Filed: September 26, 2024
    Publication date: April 3, 2025
    Applicant: Japan Display Inc.
    Inventors: Hajime WATAKABE, Masashi TSUBUKU, Kentaro MIURA, Takeshi SAKAI, Akihiro HANADA, Masahiro WATABE
  • Patent number: 12200435
    Abstract: A sound reproduction device includes a cabinet and a loudspeaker disposed inside the cabinet, the cabinet includes a baffle including a plurality of through holes provided in a ring-shaped area, and the loudspeaker is disposed in an orientation in which sound is emitted toward the plurality of through holes.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: January 14, 2025
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Isao Kakuhari, Nobuhiko Washio, Takeshi Sakai
  • Patent number: 12176438
    Abstract: According to one embodiment, a semiconductor device includes an oxide semiconductor. The oxide semiconductor includes a first edge portion and a second edge portion intersecting a gate electrode, a first area overlapping the gate electrode, a second area along the first edge portion, a third area along the second edge portion, a fourth area the first edge portion, a fifth area along the second edge portion, a sixth area surrounded by the first area, the second area and the third area, and a seventh area surrounded by the first area, the fourth area and the fifth area. The first area, the second area and the third area, the fourth area and the fifth area have a higher resistivity than those of the sixth area and the seventh area.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: December 24, 2024
    Assignee: JAPAN DISPLAY INC.
    Inventors: Hajime Watakabe, Kentaro Miura, Toshinari Sasaki, Takeshi Sakai, Akihiro Hanada, Masashi Tsubuku
  • Patent number: 12081155
    Abstract: A motor control device includes an abnormality determination unit that determines the presence of any abnormality in a current detector. The abnormality determination unit includes, for example, a U-phase abnormality determination device. The U-phase abnormality determination device calculates, as a voltage command threshold, a value obtained by adding a dead time voltage error, which is a voltage error occurring due to a dead time, to an ideal voltage command threshold, which is a value obtained by multiplying a prescribed reference current value by a motor resistance value, and outputs a signal indicating an abnormality in the current detector when the effective value of a voltage command value is equal to or greater than the voltage command threshold and the effective value of a current detection value is equal to or less than a current detection threshold that is lower than the reference current value.
    Type: Grant
    Filed: October 25, 2022
    Date of Patent: September 3, 2024
    Assignee: OKUMA CORPORATION
    Inventors: Ai Kojima, Yuji Uchida, Takeshi Sakai
  • Publication number: 20240280970
    Abstract: A controller for a machine tool that moves a feed shaft moving a cutting tool and a workpiece to thereby cut the workpiece. The controller includes a command generator outputting a moving command to shift the feed shaft in a feeding direction while allowing the feed shaft to oscillate along the feeding direction, a position controller outputting a velocity command, a velocity controller outputting a torque command, a current controller controlling motor line current, and an inversion compensation calculator calculating a compensation amount compensating for a tracking delay caused by inversion of a moving direction of the feed shaft and adding the compensation amount to the moving command etc. for inversion compensation. The controller does not perform the inversion compensation unless the feeding direction is inverted, in spite of inversion of the moving direction of the feed shaft due to oscillation.
    Type: Application
    Filed: February 12, 2024
    Publication date: August 22, 2024
    Inventors: Shunichi TAKASHIMA, Takeshi SAKAI
  • Publication number: 20240248361
    Abstract: A display device comprising a transistor and a display element over the transistor, wherein the transistor includes a gate electrode on an insulating surface, a gate insulating layer on the gate electrode, and source/drain electrodes on the oxide semiconductor layer and the gate insulating layer, each including a first conductive layer containing nitrogen and a second conductive layer on the first conductive layer, and an insulating layer contains oxygen on the oxide semiconductor layer and the source/drain electrodes.
    Type: Application
    Filed: March 4, 2024
    Publication date: July 25, 2024
    Applicant: Japan Display Inc.
    Inventors: Masashi TSUBUKU, Takeshi SAKAI, Tatsuya TODA
  • Publication number: 20240194795
    Abstract: The purpose of the invention is to form the TFT of the oxide semiconductor, in which influence of variation in mask alignment is suppressed, thus, manufacturing a display device having a TFT of stable characteristics. The concrete measure is as follows. A display device including plural pixels, each of the plural pixels having a thin film transistor (TFT) of an oxide semiconductor comprising: a width of the oxide semiconductor in the channel width direction is wider than a width of the gate electrode in the channel width direction.
    Type: Application
    Filed: February 12, 2024
    Publication date: June 13, 2024
    Applicant: Japan Display Inc.
    Inventors: Takeshi SAKAI, Yuichiro HANYU, Masahiro WATABE
  • Publication number: 20240159970
    Abstract: An optical waveguide device that enables a location in which an optical loss such as a propagation loss or a coupling loss occurs to be easily specified is provided. An optical waveguide device includes a substrate 1 on which an optical waveguide 2 is formed, and a grating 6 formed in a part of the optical waveguide 2 or a grating 6 connected to a monitoring optical waveguide 5 that merges with or branches from a part of the optical waveguide 2, in which inputting a light wave into the optical waveguide or outputting at least a part of the light wave propagating through the optical waveguide is performed through the grating 6.
    Type: Application
    Filed: March 30, 2022
    Publication date: May 16, 2024
    Applicant: SUMITOMO OSAKA CEMENT CO., LTD.
    Inventors: Takeshi SAKAI, Toshio KATAOKA, Yu KATAOKA
  • Publication number: 20240147154
    Abstract: An acoustic device includes a first acoustic unit and a second acoustic unit. The first acoustic unit includes: a first loudspeaker module that includes a first sound emitting surface provided to face the second acoustic unit; and a first sound absorbing module that includes a first sound absorbing surface provided around the first sound emitting surface to face the second acoustic unit. The second acoustic unit includes: a second loudspeaker module that includes a second sound emitting surface provided to face the first acoustic unit; and a second sound absorbing module that includes a second sound absorbing surface provided around the second sound emitting surface to face the first acoustic unit.
    Type: Application
    Filed: December 7, 2023
    Publication date: May 2, 2024
    Inventors: Akihisa KAWAMURA, Satoshi TAKAYAMA, Takeshi SAKAI
  • Patent number: 11935967
    Abstract: The purpose of the invention is to form the TFT of the oxide semiconductor, in which influence of variation in mask alignment is suppressed, thus, manufacturing a display device having a TFT of stable characteristics. The concrete measure is as follows. A display device including plural pixels, each of the plural pixels having a thin film transistor (TFT) of an oxide semiconductor comprising: a width of the oxide semiconductor in the channel width direction is wider than a width of the gate electrode in the channel width direction.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: March 19, 2024
    Assignee: Japan Display Inc.
    Inventors: Takeshi Sakai, Yuichiro Hanyu, Masahiro Watabe
  • Publication number: 20240086146
    Abstract: A content playback device includes: a network interface that receives the current perceived temperature information for a person in a specific area from a server via a communication network; a memory that stores the perceived temperature information and date information indicating the current date; and a central processing unit (CPU) that causes the memory to store the perceived temperature information received by the network interface, selects playback content from a plurality of pieces of content, based on the perceived temperature information and the date information, and plays back the playback content.
    Type: Application
    Filed: November 17, 2023
    Publication date: March 14, 2024
    Inventors: Toya Kitagawa, Nobuhiko WASHIO, Takeshi SAKAI
  • Patent number: 11927859
    Abstract: A display device comprising a transistor and a display element over the transistor, wherein the transistor includes a gate electrode on an insulating surface, a gate insulating layer on the gate electrode, and source/drain electrodes on the oxide semiconductor layer and the gate insulating layer, each including a first conductive layer containing nitrogen and a second conductive layer on the first conductive layer, and an insulating layer contains oxygen on the oxide semiconductor layer and the source/drain electrodes.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: March 12, 2024
    Assignee: Japan Display Inc.
    Inventors: Masashi Tsubuku, Takeshi Sakai, Tatsuya Toda
  • Patent number: 11817309
    Abstract: Provided are: a method of producing heated ozone water, the method capable of producing heated ozone water having an extremely high ozone concentration by suppressing a reduction in the ozone concentration in high-concentration heated ozone water; heated ozone water; and a semiconductor wafer-cleaning liquid using the heated ozone water. A method of producing heated ozone water obtained by dissolving ozone in pure water, the method being characterized by including: adjusting a pH of the pure water to 3 or less by adding acid to the pure water; to obtain an acid water, dissolving an ozone gas in the acid water; and heating the pure water, the acid water or the ozone water, to 60° C. or more.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: November 14, 2023
    Assignees: TOHOKU UNIVERSITY, NOMURA MICRO SCIENCE CO., LTD.
    Inventors: Yasuyuki Shirai, Takeshi Sakai, Takayuki Jizaimaru
  • Publication number: 20230292551
    Abstract: A display device includes a light-emitting element; a first transistor and a second transistor connected in series between the light-emitting element and a driving power line; a third transistor electrically connected to a gate electrode of the first transistor; and a fourth transistor connected in parallel between a drain electrode of the first transistor and the light-emitting element, wherein a ratio of a channel width W1 to a channel length L1 of the first transistor (a W1/L1 ratio) and a ratio of a channel width W2 to a channel length L2 of the second transistor (a W2/L2 ratio) are larger than a ratio of a channel width W3 to a channel length L3 of the third transistor (a W3/L3 ratio) and a ratio of a channel width W4 to a channel length L4 of the fourth transistor (a W4/L4 ratio).
    Type: Application
    Filed: March 1, 2023
    Publication date: September 14, 2023
    Applicant: Japan Display Inc.
    Inventors: Masashi TSUBUKU, Takeshi SAKAI, Kentaro MIURA, Hajime WATAKABE, Takaya TAMARU, Hiroshi TABATAKE, Yutaka UMEDA
  • Patent number: 11710746
    Abstract: The semiconductor device comprises a gate electrode, a first gate insulating film overlapping a part of the side surface and the upper surface of the gate electrode, a second gate insulating film overlapping the upper surface of the gate electrode, a semiconductor film provided on the upper surface of the second gate insulating film and overlapping the gate electrode and a first terminal and a second terminal overlapping the upper surface of the semiconductor film. In a plan view, a first region is a region where the semiconductor film overlaps the upper surface of the first gate insulating film and the second gate insulating film between the first terminal and the second terminal, and a third region is a region that overlaps both a part of the upper surface of the gate electrode and the second gate insulating film and does not overlap the first gate insulating film.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: July 25, 2023
    Assignee: JAPAN DISPLAY INC.
    Inventor: Takeshi Sakai
  • Patent number: 11659735
    Abstract: The semiconductor device includes a first gate electrode, a first gate insulating film, a semiconductor film, a first electrode, a second electrode, a second gate insulating film, and a second gate electrode. The first gate insulating film is located over the first gate electrode. The semiconductor film is located over the first gate insulating film and overlaps with the first gate electrode. The first electrode and the second electrode are each located over and in contact with the semiconductor film. The second gate insulating film is located over the first electrode and the second electrode. The second gate electrode is located over the second gate insulating film and overlaps with the second electrode and the first gate electrode. The first electrode is completely exposed from the second gate electrode.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: May 23, 2023
    Assignee: JAPAN DISPLAY INC.
    Inventor: Takeshi Sakai
  • Publication number: 20230125931
    Abstract: A sound reproduction device includes a cabinet and a loudspeaker disposed inside the cabinet, the cabinet includes a baffle including a plurality of through holes provided in a ringshaped area, and the loudspeaker is disposed in an orientation in which sound is emitted toward the plurality of through holes.
    Type: Application
    Filed: May 24, 2021
    Publication date: April 27, 2023
    Inventors: Isao KAKUHARI, Nobuhiko WASHIO, Takeshi SAKAI
  • Publication number: 20230126273
    Abstract: A motor control device includes an abnormality determination unit that determines the presence of any abnormality in a current detector. The abnormality determination unit includes, for example, a U-phase abnormality determination device. The U-phase abnormality determination device calculates, as a voltage command threshold, a value obtained by adding a dead time voltage error, which is a voltage error occurring due to a dead time, to an ideal voltage command threshold, which is a value obtained by multiplying a prescribed reference current value by a motor resistance value, and outputs a signal indicating an abnormality in the current detector when the effective value of a voltage command value is equal to or greater than the voltage command threshold and the effective value of a current detection value is equal to or less than a current detection threshold that is lower than the reference current value.
    Type: Application
    Filed: October 25, 2022
    Publication date: April 27, 2023
    Inventors: Ai KOJIMA, Yuji UCHIDA, Takeshi SAKAI
  • Publication number: 20230101477
    Abstract: Provided is a stripping method capable of stripping a resist while suppressing the time and cost of processing required for stripping, while giving sufficient consideration to the load on the environment. The resist stripping method is a method for stripping a resist film-formed on a substrate, including: a pretreatment step of exposing the resist to a heated steam in a predetermined temperature range for a predetermined time; and a stripping step of stripping the resist exposed to the heated steam in the pretreatment step by using a resist stripping liquid, wherein the predetermined temperature range and the predetermined time are set according to the resist.
    Type: Application
    Filed: December 7, 2022
    Publication date: March 30, 2023
    Applicants: NOMURA MICRO SCIENCE CO., LTD., TOHOKU UNIVERSITY
    Inventors: Takayuki Jizaimaru, Takao Funakoshi, Yasuyuki Shirai, Hisashi Fujimoto, Takeshi Sakai
  • Publication number: 20230058988
    Abstract: According to one embodiment, a transistor includes a gate electrode, an oxide semiconductor layer which overlaps the gate electrode and including a central portion and an end portion, and a source electrode and a drain electrode each connected to the oxide semiconductor layer, wherein an oxidation degree of the end portion is lower than an oxidation degree of the central portion, and a length of the gate electrode overlapping the central portion is greater than a length of the gate electrode overlapping the end portion.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 23, 2023
    Applicant: Japan Display Inc.
    Inventors: Akihiro HANADA, Hajime WATAKABE, Takeshi SAKAI