Abstract: The overlapping portions of an image composed of partial images projected on a dome-shaped screen from image projecting means are shaded in light by means of light shading mechanisms which are provided for the corresponding image projecting means. Each light shading mechanism includes at least one light shading plate with a notch formed therein, and after projection, the notch is defined by a first curved edge line corresponding to a center line of a first over-lapping portion of the overlapping portions and a second curved edge line corresponding to a center line of a second overlapping portion of the overlapping portions. As a result, the luminance of the image projected on the dome-shaped screen can be easily adjusted in the same manner as a planer screen.

Abstract: An inkjet printer includes: a recording head which includes jet openings for jetting ink; a sensor for detecting a jet opening causing jetting failure among the jet openings; a sucking mechanism for sucking the ink from each jet opening; a comparing section for comparing number of the detected jet opening causing jetting failure with predetermined number; and a control section for performing a sucking process where the sucking mechanism performs a sucking operation, for performing an examination process to count the jet opening causing jetting failure by the detection of the sensor and by simulated jetting of each jet opening, for performing a comparing process where the comparing section performs a comparing operation after the examination process, and for re-performing the examination process without performing the sucking process when judged in the comparing process that the number of the jet opening causing jetting failure is more than the predetermined number.

Abstract: The present invention has been conceived in view of the above described situation, and an object of the invention is to provide an information processing device, data transfer method and information storage medium that can commence data transfer to an I/O device immediately, and can stably exhibit data transfer performance. In an information processing device provided with hardware for sharing an address translation table, for translating logical addresses of a memory to physical addresses, between a main processor and a sub-processor, one of the sub-processors is caused to function as means for receiving a transfer request designating a logical address of the memory, means for translating the logical address that has been designated in the transfer request to a physical address using the shared address translation table, and means for executing transfer processing for data stored in the memory 14 according to the translated physical address.

Abstract: An electro-optical composite connector includes a receptacle connector including a receptacle housing to be mounted on a first board, a receptacle shell for covering the receptacle housing, and a receptacle terminal arranged on the receptacle housing; and a plug connector including a plug housing for holding an optical fiber, a plug shell for covering the plug housing, and an optical module to be connected to the optical fiber. The optical module includes a second board; a light receiving/emitting element mounted on one surface of the second board; at least one of a plug terminal and a land mounted on the one surface of the second board for transmitting a signal relative to the receptacle terminal; and a grounding surface formed on the other surface of the second board opposite to the one surface. The grounding surface is electrically connected to an inner wall of the plug shell.

Abstract: A photoelectric combined connector includes a first connector and a second connector. The first connector includes a first housing and a first electrical terminal disposed in the first housing. The second connector includes a second housing, a board disposed in the second housing and having a photoelectric conversion unit, and a second electrical terminal disposed in the second housing. The second electrical terminal includes a fitted-in portion into which a part of the board is fitted when the board is attached to the second housing. When the first connector is connected to the second connector, the first electrical terminal of the first connector electrically contacts with the second electrical terminal of the second connector. Through the contact, the first electrical terminal of the first connector electrically contacts with the photoelectric conversion unit of the second connector.

Abstract: This invention can play back a smooth moving image in both normal and slow playback modes in consideration of the human visual recognition level, even when moving image data to be decoded (played back) is recorded (encoded) at a high frame rate. To this end, in this invention, respective frames, which form a moving image at 60 frames/sec, are compressed to be independently decodable. In the normal playback mode, since frames are played back using one of two frames (decimating one of two frames), a moving image is played back at 30 frames/sec which can assure sufficiently high image quality as a moving image. On the other hand, in the slow play back mode, since the number of frames to be decimated is set to be zero, and 60 frames are played back for 2 sec, a moving image is played back at the same frame rate of 30 frames/sec as that in the normal playback mode.

Abstract: An electro-optical composite connector includes a receptacle connector including a receptacle housing to be mounted on a first board, a receptacle shell for covering the receptacle housing, and a receptacle terminal arranged on the receptacle housing; and a plug connector including a plug housing for holding an optical fiber, a plug shell for covering the plug housing, and an optical module to be connected to the optical fiber. The optical module includes a second board; a light receiving/emitting element mounted on one surface of the second board; at least one of a plug terminal and a land mounted on the one surface of the second board for transmitting a signal relative to the receptacle terminal; and a grounding surface formed on the other surface of the second board opposite to the one surface. The grounding surface is electrically connected to an inner wall of the plug shell.

Abstract: A processor is provided which has a modular organization including at least one local store operable to store data and instructions for execution, at least one functional unit operable to execute instructions on data provided from the local store, and at least one issue logic unit operable to convert instructions provided from the local store into operations of the functional unit for executing the instructions. The at least one issue logic unit may be operable to decode a unitary instruction provided from the local store to simultaneously operate all of the functional units according to the unitary instruction. Each issue logic unit may be operable to decode multiple instructions to separately operate first and second subsets of the plurality of functional units according to respective ones of the multiple instructions.

Abstract: An ink jet printer having: a main tank to store ink; a recording head to form an image on a recording medium by jetting the ink from a nozzle; an ink supply path to supply the ink to the recording head from the main tank; a sub tank to temporarily store the ink supplied from the main tank, the sub tank being provided in the middle of the ink supply path; an ink supply valve to control to supply or stop supplying the ink from the main tank to the sub tank by an opening or closing the ink supply valve, the ink supply valve being provided between the main tank and the sub tank on the ink supply path; and a control unit to measure a cumulative time in which the ink supply valve becomes an opened state, and estimate a remaining ink amount in the main tank.

Abstract: The brushless motor includes: a housing; a stator which is stored and fixed in the housing; a rotor which is rotatably arranged inside the stator; a bracket which is fixed to the housing; a rotation detector which is fixed to the bracket and the housing and detects a rotation position of the rotor; and an engagement device which restrains movement of the bracket along a circumferential direction with respect to the housing.

Abstract: This brushless motor includes: stators respectively having wires and cores around which the wires are respectively wound; a housing which houses the stators; a rotor rotatably attached to the housing; and a bracket having conductive bodies to which terminal leading lines of the wires are respectively connected and an insulating body supporting the conductive bodies, and installed in an opening of the housing; wherein the conductive bodies are insert-molded to the insulating body.

Abstract: A DMA controller (DMAC) for handling a list DMA command in a computer system is provided. The computer system has at least one processor and a system memory, the list DMA command relates to an effective address (EA) of the system memory, and the at least one processor has a local storage. The DMAC includes a DMA command queue (DMAQ) coupled to the local storage and configured to receive the list DMA command from the local storage and to enqueue the list DMA command. An issue logic is coupled to the DMAQ and configured to issue an issue request to the DMAQ. A request interface logic (RIL) is coupled to the DMAQ and configured to read the list DMA command based on the issue request. The RIL is further coupled to the local storage and configured to send a fetch request to the local storage to initiate a fetch of a list element of the list DMA command from the local storage to the DMAQ.

Abstract: The present invention provides for a system comprising a DMA queue configured to receive a DMA command comprising a tag, wherein the tag belongs to one of a plurality of tag groups. A counter couples to the DMA queue and is configured to increment a tag group count of the tag group to which the tag belongs upon receipt of the DMA command by the DMA queue and to decrement the tag group count upon execution of the DMA command. A tag group count status register couples to the counter and is configured to store the tag group count for each of the plurality of tag groups. And the tag group count status register is further configured to receive a request for a tag group status and to respond to the request for the tag group status.

Abstract: An information processing apparatus having a fat tree structure, in which signal transmission across node columns managed by respective processor units is performed through end point bridges included in bridge chips. In this transmission method, the bridge chips perform routing by using node IDs that are given to the respective node columns and levels that indicate the hierarchical depths of the bridge chips, thereby selecting the shortest routes of signals.

Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

Abstract: A method, an apparatus, and a computer program are provided for controlling memory access. Direct Memory Access (DMA) units have become commonplace in a number of bus architectures. However, managing limited system resources has become a challenge with multiple DMA units. In order to mange the multitude of commands generated and preserve dependencies, embedded flags in commands or a barrier command are used. These operations then can control the order in which commands are executed so as to preserve dependencies.

Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

Abstract: A system configuration includes a processing element (PE), an input/output (I/O) interface device and a shared memory. The PE further includes at least one processing unit (PU) and one, or more, attached processing units (APUs). At least one of the APUs performs an I/O function by reading data from, and writing data to, an external device coupled to the I/O interface device. Data is exchanged between the APU and the I/O interface device via the shared memory using a data level synchronization mechanism.

Abstract: A system and method are provided for setting up a direct memory access for a first processor. The system includes the first processor and a local memory. The local memory is coupled to the first processor. A first direct memory access controller (DMAC) is coupled to the first processor and the local memory. A system memory is in communication with the first DMAC. A second processor is in communication with the first DMAC such that the second processor sets up the first DMAC to handle data transfer between the local memory and the system memory. The second processor is interrupted when the first DMAC finishes handling the data transfer.

Abstract: A shock absorbing structure of a two-wheeled vehicle capable of sufficiently absorbing shock and desirably maintain the steerability of the two-wheeled vehicle. The structure includes a shock absorbing member projecting from a front wheel, wherein the shock absorbing member is crashed when the vehicle collides with an obstacle so as to absorb shock. A ceiling wall of the shock absorbing member is located at such a position that the ceiling wall does not block a forward viewing area for a driver. A center of a leading end contact surface of the shock absorbing member is located at a position higher than a vertical position of a center of gravity G of both a motorcycle and the driver, and right and left side surfaces of the shock absorbing member are offset to a center of a vehicular body from right and left side surfaces of the motorcycle.