Abstract: An objective of the present invention is to secure the continuity of the communication between a client device and a standby server device, when a failure occurs and switch to the standby device is performed. A communication processing unit of the client device establishes connection with a plurality of server devices simultaneously by transmitting a UDP packet to the plurality of server devices by multicast. After establishing the connection, data of the application is transmitted by multicast to the plurality of the server devices. In the even of a failure, a standby server device receives the data packet multicast from the client device to continue the inter-application communication.

Abstract: This invention enables to generate encoded data without noticeable image quality degradation when reproducing an image at a lower resolution not to mention the original resolution. To accomplish this, when setting is done to transmit an image captured by a digital camera to a network, code stream forming information CF is set to “2” to arrange the encoded data of each tile in a resolution order. To suppress image quality degradation when reproducing at an intermediate resolution, stream conversion information SC is set to “2”. When encoding image data in compression processing, block overlap processing of suppressing discontinuity of data at the boundary between adjacent blocks is executed as many times as the count set in the stream conversion information. The obtained encoded data is arranged in accordance with the code stream forming information CF and output.

Abstract: Transparency of resources is provided and ordering in an access is guaranteed between nodes on a computer network. In an information processing system in which a plurality of processor units are connected to each other by a switch, a global address space is introduced into which effective addresses of the processor units are mapped and which is shared by the plurality of processor units. In response to an access request packet issued by a processor unit and designating an effective address of a target node, a bridge for routing an input and output bus of a processor unit to an input and output bus of the switch converts the effective address of the target node into a global address by appending to the packet a node identification number identifying the target node, and outputs the access request packet designating the global address to the switch. After an access request packet for a write operation is output, the bridge confirms whether the write operation is completed in a target node.

Abstract: An ebullient cooling device having a simple structure and capable of limiting the bubbles to an appropriate volume. The ebullient cooling device for cooling a heat generating element is provided with a plurality of vertically arranged cooling channels comprising a lower channel (2), a middle channel (3) and un upper channel (4). Each cooling channel has cooling fins (12) for guiding a refrigerant to flow in a vertical direction, and a vapor discharge path (16) formed at the side of the cooling fins (12) that is opposite the side in contact with the heat generating element. Furthermore, flow path partition/vapor discharge guiding plates (18) are provided between the cooling channels so that the bubbles that have been generated are guided to the vapor discharge path (16) and prevented from moving into the subsequent cooling channel.

Abstract: A cooling system has a configuration in which a cooling system for an inverter device and a motor generator also serves as a cooling system for a battery. In this configuration, a control device performs temperature-raising control of the battery when a battery temperature is below a prescribed temperature lower limit value. The control device controls an operation of a switching valve such that cooling water from a cooling medium path is outputted to a bypass path. Further, if a cooling water temperature is lower than a prescribed temperature, the control device controls the inverter device such that a power loss during a switching operation in a switching element included in the inverter device becomes larger than a power loss during normal control. As a result, the cooling system having a small-sized, low-cost configuration rapidly recovers capacity decline of the battery, which occurs at low temperatures.

Abstract: A spectroscope includes an emitting portion from where light is output, a dispersive element which is disposed on a side of the light emitting portion, to which the light is output, an incidence portion on which, light dispersed by the dispersive element is incident, and a temperature-compensating element which is disposed between the emitting portion and the incidence portion, and which is such that, an angle of incidence of the light dispersed on the incidence portion becomes almost constant with respect to a change in temperature in an operating temperature range. Moreover, the optical apparatus has such spectroscope in which temperature is compensated.

Abstract: An electric storage device is provided with a battery cell, a collector foil having a first metal plate and a second metal plate laminated together, and a voltmeter for measuring potential difference between the first metal plate and the second metal plate. The first metal plate and the second metal plate are formed of mutually different metals. The collector foil is arranged to be in contact with the battery cell.

Abstract: A downstream port 22 of a bridge 20 connecting a processor unit and a peripheral device acknowledges access from the peripheral device via one of a plurality of downstream channels available for access by the peripheral device to a memory of the processor unit, the downstream channels being virtual channels provided for interfacing with the peripheral device. The router 24 routes the access to upstream channels each assigned a memory bandwidth available for access to the memory, the upstream channels being virtual channels supported by the processor unit. In this process, the router refers to a table storing identifiers of the downstream channels and identifiers of the upstream channels in association with each other so as to allocate to the peripheral device the upstream channel corresponding to the downstream channel used by the peripheral device, in response to the access from the peripheral device.

Abstract: This invention enables to generate encoded data without noticeable image quality degradation when reproducing an image at a lower resolution not to mention the original resolution. An image a digital camera can capture takes three sizes L, M, and S. When the size L is designated, stream conversion information SC is set to “2”. When the size M is designated, the stream conversion information SC is set to “1”. When the size S is designated, the stream conversion information SC is set to “0”. When encoding image data in compression processing, block overlap processing of suppressing discontinuity of data at the boundary between adjacent blocks is executed as many times as the count set in the stream conversion information.

Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A processing system for processing computer tasks is also provided. A first processor is of a first processor type and a number of second processors are of a second processor type. One of the second processors manages process scheduling of computing tasks by providing tasks to at least one of the first and second processors.

Abstract: A computer which takes over a task managed by a server apparatus from another computer which occupies the task, the computer including, a processor to detect an error of the other computer, to transmit, when an error of the another computer is detected, a task relaying request for taking over the task to the server apparatus, and to allow when a permission of the takeover of the task is received from the server apparatus processes of application programs in standby states in the computer to occupy the task.

Abstract: A storage medium storing a program, in inter-application communication that is performed between a first application operating on a first node and a second application operating on a second node, for making the first node perform processes by transmitting a same packet simultaneously to all the communication paths, the processes including: a trouble monitoring session establishing process in which, whether or not a trouble monitoring session has already been established between a first communication control unit and a second communication control unit is checked; an inter-application communication session establishing process in which, a request for establishing the inter-application communication session is performed to the second application and the inter-application communication session is established; and a trouble monitoring communication process in which trouble monitoring communication is performed using only necessary information for trouble monitoring in the trouble monitoring session and at a short

Abstract: In a brushless motor for an electric power steering device having a configuration of 2 poles and 3 slots, or of an integral multiple thereof, a stator coil is supplied with current containing a higher harmonic component. A difference of 0.5% to 1.5% is provided between the higher harmonic component content rate of the stator coil current and the higher harmonic component content rate of the induced electromotive force generated in the stator coil with rotation of a permanent magnet, thereby mitigating the influence by an armature reaction generated in the induced electromotive force to reduce torque ripples. The difference between the higher harmonic component content rates is set on the basis of a change that occurs in the induced electromotive force due to the armature reaction at a time of supplying electricity to the armature coil.

Abstract: A simulation apparatus is composed of an integrated plant model process unit 1, virtual ECUs 50A to 50C that simulate other controllers, and a simulation management unit 2 that manages the execution of an input and output process to a real ECU 300, a process by the integrated plant model process unit 1, and a process by the virtual ECUs 50A to 50C, and so on, and the simulation management unit 2 causes the integrated plant model process unit 1, the virtual ECUs 50A to 50C, and so on to execute the processes required for the operation of the real ECU 300 during a given period on the basis of the operation of the real ECU 300.

Abstract: Disclosed is a procedure or design approach for functional modules that may be used in connection with a multiprocessor integrated circuit chip. The approach includes keeping the dimensions of each module substantially the same and having the bus, power, clock and I/O connection configured the same on all modules. Further requirements for ease of use are to generalize the capability of each module as much as possible and to decentralize functions such as testing to be primarily performed within each module. The use of such considerations or rules substantially eases the design of a given type of custom chips, and based upon an initial chip design greatly facilitates the design of further custom chips, similar in application, but subsequent to the successful completion of the initial chip.

Abstract: A driving apparatus includes a rotating electrical machine; an inverter capable of supplying electric power to the rotating electrical machine; a containing case; a coolant circuit distributing coolant capable of cooling the inverter and the rotating electrical machine; a cooling mechanism, which is provided in the coolant circuit, is contained in the containing case, and is capable of cooling the rotating electrical machine and the inverter; and a supplying pipe capable of supplying the cooling mechanism with the coolant circulating in the cooling circuit.

Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A processing system for processing computer tasks is also provided. A first processor is of a first processor type and a number of second processors are of a second processor type. One of the second processors manages process scheduling of computing tasks by providing tasks to at least one of the first and second processors.

Abstract: Methods and apparatus provide for interconnecting one or more multiprocessors and one or more external devices through one or more configurable interface circuits, which are adapted for operation in: (i) a first mode to provide a coherent symmetric interface; or (ii) a second mode to provide a non-coherent interface.

Abstract: There is provided a technique of accessing a memory of a processor from a peripheral device, thereby the security is ensured while efficiency is being pursued. An address converter 14 includes an address conversion table for converting an effective address into a physical address. The address conversion table stores the effective address to which an area in a memory of a processor unit 10 is allocated to each peripheral device 30 and identification information of an access source to which access permission is given, in association with each other. When the peripheral device 30 accesses, the address converter 14 determines to permit access to the effective address under the condition that the device identification information, included in an access request packet, by which the peripheral device 30 can be uniquely identified, matches the identification information of the access source corresponding to the effective address, in the address conversion table, designated by the access request packet.

Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A processing system for performing graphics processing is also provided. A first processor is of a first processor type and a number of second processors are of a second processor type. One of the second processors can perform graphics processing on a first set of graphics data to generate a second set of graphics data, and another of the second processors can perform graphics processing on the second set to generate a third set of graphics data.