Abstract: The present invention has been conceived in view of the above described situation, and an object of the invention is to provide an information processing device, data transfer method and information storage medium that can commence data transfer to an I/O device immediately, and can stably exhibit data transfer performance. In an information processing device provided with hardware for sharing an address translation table, for translating logical addresses of a memory to physical addresses, between a main processor and a sub-processor, one of the sub-processors is caused to function as means for receiving a transfer request designating a logical address of the memory, means for translating the logical address that has been designated in the transfer request to a physical address using the shared address translation table, and means for executing transfer processing for data stored in the memory 14 according to the translated physical address.

Abstract: An apparatus and a computer program product are provided for completing a plurality of (direct memory access) DMA commands in a computer system. It is determined whether the DMA commands are chained together as a list DMA command. Upon a determination that the DMA commands are chained together as a list DMA command, it is also determined whether a current list element of the list DMA command is fenced. Upon a determination that the current list element is not fenced, a next list element is fetched and processed before the current list element has been completed.

Abstract: A brushless motor has rotor cores dividedly formed as plural sections in an axial direction, segment magnets secured to outer circumferential surfaces of the rotor cores, and magnet holders secured to the rotor cores, respectively, for holding the segment magnet. Each of the rotor cores has holder-positioning grooves to which holder arms are fitted, and bridge parts formed corresponding to the holder positioning grooves. Each of the magnet holders has joint grooves fitted in the bridge parts and displaced from the holder arms by a step angle, the bridge parts being fitted in the joint grooves, thereby assembling a rotor.

Abstract: Methods and apparatus provide for interconnecting one or more multiprocessors and one or more external devices through one or more configurable interface circuits, which are adapted for operation in: (i) a first mode to provide a coherent symmetric interface; or (ii) a second mode to provide a non-coherent interface.

Abstract: Methods and apparatus provide for sending a data command from a first of a plurality of devices to a first address concentrator within a first of a plurality of processing systems; selecting one of the other processing systems, the selected processing system having data addressed by the data command stored therein; sending the data command to a first address concentrator of the selected processing system; and broadcasting the data command from the first address concentrator of the selected processing system to a second address concentrator in each of the processing systems.

Abstract: A driving gear of a vehicle comprising a motor generator (MG2), a power control unit (21) for controlling the motor generator (MG2), and a case for containing the motor generator (MG2) and the power control unit (21). The power control unit (21) comprises a first inverter for driving the motor generator (MG2), and a voltage converter for applying power supply voltage to the first inverter after stepping it up. The voltage converter includes a reactor (L1). Heat of the reactor (L1) is dissipated using lubricant touching the reactor (L1) and the case as heat transfer agent. A circulation path of lubricant is formed in the case and the reactor is arranged on the circulation path.

Abstract: Methods and apparatus provide for interconnecting one or more multiprocessors and one or more external devices through one or more configurable interface circuits, which are adapted for operation in: (i) a first mode to provide a coherent symmetric interface; or (ii) a second mode to provide a non-coherent interface.

Abstract: A spectroscope includes an emitting portion from where light is output, a dispersive element which is disposed on a side of the light emitting portion, to which the light is output, an incidence portion on which, light dispersed by the dispersive element is incident, and a temperature-compensating element which is disposed between the emitting portion and the incidence portion, and which is such that, an angle of incidence of the light dispersed on the incidence portion becomes almost constant with respect to a change in temperature in an operating temperature range. Moreover, the optical apparatus has such spectroscope in which temperature is compensated.

Abstract: A driving apparatus includes a rotating electrical machine; an inverter capable of supplying electric power to the rotating electrical machine; a containing case; a coolant circuit distributing coolant capable of cooling the inverter and the rotating electrical machine; a cooling mechanism, which is provided in the coolant circuit, is contained in the containing case, and is capable of cooling the rotating electrical machine and the inverter; and a supplying pipe capable of supplying the cooling mechanism with the coolant circulating in the cooling circuit.

Abstract: The thermal printer of the present invention is a thermal printer for printing on a print medium by thermally transferring an ink ribbon by means of a thermal head, wherein the thermal printer comprises a density controller for keeping the print density of the thermal head low in low-temperature control for raising the print density at low temperatures. The density controller comprises a density calculator for calculating a density evaluation value by finding an average gradation value of print data for each of a plurality of dots included in the predetermined region, a comparator for comparing the calculated density evaluation value with a predetermined value, and an adjuster for adjusting, on the basis of this comparison result, the print density in driving and printing with the thermal head to a low value for print data of high gradation exceeding a predetermined gradation value in print data on a printed line when the density evaluation value exceeds a predetermined value.

Abstract: An encoding apparatus encodes an image by tile in a smallest possible size while suppresses segmentation of a specific region in the image into tiles. Vertical lines at left and right ends of n-th face region are defined as boundary candidate vertical lines Lh(n) and Lm(n), and horizontal lines at upper and lower ends of the n-th region, as boundary candidate horizontal lines Lu(n) and Ls(n). A divider determines a horizontal line of another region existing within the range of the horizontal lines Lu(n) and Ls(n) of the n-th region as a line to be deleted. Further, the divider determines a vertical line of another region existing within the range of the vertical lines Lh(n) and Lm(n) as a line to be deleted. This processing is performed to the final region, then image data is divided using horizontal and vertical lines except the lines determined as lines to be deleted.

Abstract: The present invention provides a method and apparatus for creating memory barriers in a Direct Memory Access (DMA) device. A memory barrier command is received and a memory command is received. The memory command is executed based on the memory barrier command. A bus operation is initiated based on the memory barrier command. A bus operation acknowledgment is received based on the bus operation. The memory barrier command is executed based on the bus operation acknowledgment. In a particular aspect, memory barrier commands are direct memory access sync (dmasync) and direct memory access enforce in-order execution of input/output (dmaeieio) commands.

Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

Abstract: Methods and apparatus provide for adding a base address to an external address to produce first intermediate address; using only a first portion of the first intermediate address as a pointer to select one of a plurality of entries in a segment table, each entry of the segment table representing a different segment of a memory using at least a portion of the selected entry of the segment table as a reference to one or more of a plurality of entries in a page table, each entry in the page table including at least a portion of a physical address in the memory and belonging to a group of entries representing a page in the selected segment of the memory; using the second portion of the first intermediate address to produce a second intermediate address; and using at least a portion of the second intermediate address as a pointer directly to one of the referenced entries in the page table to obtain an at least partially translated physical address into the memory for the external address.

Abstract: Methods and apparatus provide for transferring a plurality of data blocks between a shared memory and a local memory of a processor in response to a single DMA command issued by the processor to a direct memory access controller (DMAC), wherein the processor is capable of operative communication with the shared memory and the DMAC is operatively coupled to the local memory.

Abstract: A storage medium storing a program, in inter-application communication that is performed between a first application operating on a first node and a second application operating on a second node, for making the first node perform processes by transmitting a same packet simultaneously to all the communication paths, the processes including: a trouble monitoring session establishing process in which, whether or not a trouble monitoring session has already been established between a first communication control unit and a second communication control unit is checked; an inter-application communication session establishing process in which, a request for establishing the inter-application communication session is performed to the second application and the inter-application communication session is established; and a trouble monitoring communication process in which trouble monitoring communication is performed using only necessary information for trouble monitoring in the trouble monitoring session and at a short

Abstract: Transparency of resources is provided and ordering in an access is guaranteed between nodes on a computer network. In an information processing system in which a plurality of processor units are connected to each other by a switch, a global address space is introduced into which effective addresses of the processor units are mapped and which is shared by the plurality of processor units. In response to an access request packet issued by a processor unit and designating an effective address of a target node, a bridge for routing an input and output bus of a processor unit to an input and output bus of the switch converts the effective address of the target node into a global address by appending to the packet a node identification number identifying the target node, and outputs the access request packet designating the global address to the switch. After an access request packet for a write operation is output, the bridge confirms whether the write operation is completed in a target node.

Abstract: A processor includes a CPU core which executes a user program, and a data transfer apparatus. The CPU core stores a transfer request from a user program in a specific area of a main memory, in which the transfer request specifies the virtual addresses of a transfer source and a transfer destination in a memory space allocated to the user program. The data transfer apparatus refers to the specific area of the main memory and acquires a transfer request asynchronously to processing performed by the CPU core. The data transfer apparatus then identifies physical addresses corresponding to virtual addresses specified in the transfer request. After that, the data transfer apparatus transcribes original data stored in a storage area indicated by the physical address of the transfer source, to a storage area in a cache memory related to the virtual address or physical address of the transfer destination.

Abstract: A cooling system has a configuration in which a cooling system for an inverter device and a motor generator also serves as a cooling system for a battery. In this configuration, a control device performs temperature-raising control of the battery when a battery temperature is below a prescribed temperature lower limit value. The control device controls an operation of a switching valve such that cooling water from a cooling medium path is outputted to a bypass path. Further, if a cooling water temperature is lower than a prescribed temperature, the control device controls the inverter device such that a power loss during a switching operation in a switching element included in the inverter device becomes larger than a power loss during normal control. As a result, the cooling system having a small-sized, low-cost configuration rapidly recovers capacity decline of the battery, which occurs at low temperatures.

Abstract: This invention provides a technique of easily encoding image data to generate encoded data having high image quality within a target code amount using a small memory capacity by image encoding processing of performing frequency transform and quantization of each pixel block. A frequency transform unit separates image data into low frequency band data and high frequency band data. A coefficient quantizing unit, coefficient encoder, and code amount controller operate to encode the high frequency band data within a predetermined amount. When the encoding processing of the high frequency band data has ended, the quantization parameter of the low frequency band data is set based on the generated code amount of the high frequency band data. A coefficient quantizing unit, coefficient encoder, code amount detector, and quantization parameter updating unit operate to encode the low frequency band data into codes within a low frequency band target code amount.