Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate, and a gate pad and a source pad provided above a first main surface. The silicon carbide substrate includes a first region including unit cells, a second region overlapping the gate pad, and a third region continuous with the second region. Each of the unit cells includes a contact region electrically connected to a body region, and a gate insulating film provided between a gate electrode and a drift region, the body region, and a source region. The second region has a first semiconductor region of the second conductivity type. The third region has a second semiconductor region of the second conductivity type. The first semiconductor region and the second semiconductor region are continuous with each other along the first main surface. The source region, the contact region, and the second semiconductor region are electrically connected to the source pad.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate that has first and second main surfaces and that includes a drift region being of a first-conductivity-type, a body region provided on the drift region and being of a second-conductivity-type, a source region provided on the body region and being of the first-conductivity-type, and a first electric field relaxation region being of the second-conductivity-type and including a first plane in which an impurity-concentration of the second-conductivity-type is a maximum and a second plane in which the impurity-concentration of the second-conductivity-type of 1/10 of the maximum, the second plane being closer to the second main surface than the first plane is. A distance between the first and second planes is 1.0 ?m or greater, and a distance from the first main surface to an interface between the first electric field relaxation region and the drift region is 2.0 ?m or greater.

Abstract: In the direction from the first main surface toward the second main surface through each of the second impurity region and the fourth impurity region, a concentration profile of an n-type impurity has a second relative maximum value and a fourth relative maximum value located closer to the first main surface than a position where the second relative maximum value is exhibited. The fourth relative maximum value is larger than the third relative maximum value, the third relative maximum value is larger than the second relative maximum value, and the second relative maximum value is larger than the first relative maximum value.

Abstract: A silicon carbide semiconductor device has a silicon carbide substrate, a first insulator, a first electrode, and a second electrode. The silicon carbide substrate includes a first impurity region, a second impurity region, a third impurity region, a first superjunction portion, a fourth impurity region, a fifth impurity region, a sixth impurity region, and a second superjunction portion. The first superjunction portion has a first region and a second region. The second superjunction portion has a third region and a fourth region. In a direction perpendicular to a second main surface, a bottom surface of a first trench is located between a second end surface and the second main surface and is located between a fourth end surface and the second main surface.

Abstract: An active region includes a first super junction layer and an element layer. The first super junction layer alternately has a first region and a second region. A peripheral region includes a second super junction layer, a termination layer, and an insulating layer. The second super junction layer alternately has a third region and a fourth region. The termination layer is provided on and in contact with the second super junction layer, and alternately has a fifth region and a sixth region. The fifth region is provided to correspond to the third region, and the sixth region is provided to correspond to the fourth region. An impurity concentration of the sixth region is larger than an impurity concentration of the fifth region and is 68 times or less as large as the impurity concentration of the fifth region.

Abstract: A super junction layer alternately has a first region and a second region. An element layer is provided above the super junction layer. The first region has a first portion and a second portion located between the first portion and a first main surface. The second region has a third portion in contact with the first portion and a fourth portion in contact with the second portion and located between the third portion and the first main surface. In a cross section perpendicular to the second main surface and parallel to a direction from the first region toward the second region, a width of the second portion is larger than a width of the first portion, a width of the fourth portion is smaller than a width of the third portion.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface. A gate trench is provided in the first main surface. The gate trench is defined by side surfaces and a bottom surface. The side surfaces penetrate the source region and the body region to reach the drift region. The bottom surface connects to the side surfaces. The gate trench extends in a first direction parallel to the first main surface. The silicon carbide substrate further includes an electric field relaxation region that is the second conductive type, the electric field relaxation region being provided between the bottom surface and the second main surface and extending in the first direction, and a connection region that is the second conductive type, the connection region electrically connecting a contact region to the electric field relaxation region.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate, a first electrode, and a second electrode. The silicon carbide substrate has a first main surface, a second main surface, a first impurity region, a second impurity region, and a third impurity region. The first electrode is in contact with each of the second impurity region and the third impurity region on the first main surface. The second electrode is in contact with the first impurity region on the second main surface. The second impurity region includes a first region and a second region disposed between the first region and the second main surface and in contact with the first region. An impurity concentration of the first region is more than or equal to 6×1016 cm?3.

Abstract: A silicon carbide semiconductor device has a silicon carbide substrate, a first insulator, a first electrode, and a second electrode. The silicon carbide substrate includes a first impurity region, a second impurity region, a third impurity region, a first superjunction portion, a fourth impurity region, a fifth impurity region, a sixth impurity region, and a second superjunction portion. The first superjunction portion has a first region and a second region. The second superjunction portion has a third region and a fourth region. In a direction perpendicular to a second main surface, a bottom surface of a first trench is located between a second end surface and the second main surface and is located between a fourth end surface and the second main surface.

Abstract: In the direction from the first main surface toward the second main surface through each of the second impurity region and the fourth impurity region, a concentration profile of an n-type impurity has a second relative maximum value and a fourth relative maximum value located closer to the first main surface than a position where the second relative maximum value is exhibited. The fourth relative maximum value is larger than the third relative maximum value, the third relative maximum value is larger than the second relative maximum value, and the second relative maximum value is larger than the first relative maximum value.

Abstract: A semiconductor device includes a first layer of first conductivity type and including an element region where semiconductor elements are to be formed, an annular second layer of second conductivity type formed to include a surface of the first layer, and surrounding the element region in a plan view, a third layer of second conductivity type formed in the first layer and separated more from the surface than the second layer, and sandwiching a portion of the first layer between the second and third layers, a fourth layer of second conductivity type and electrically connecting the second and third layers, and an electrode electrically connected to the fourth layer inside the second layer in the plan view. effective concentration of a second conductivity type impurity included in the second layer is higher than that of the first layer, and lower than that of the third layer.

Abstract: A semiconductor device includes a first layer of first conductivity type and including an element region where semiconductor elements are to be formed, an annular second layer of second conductivity type formed to include a surface of the first layer, and surrounding the element region in a plan view, a third layer of second conductivity type formed in the first layer and separated more from the surface than the second layer, and sandwiching a portion of the first layer between the second and third layers, a fourth layer of second conductivity type and electrically connecting the second and third layers, and an electrode electrically connected to the fourth layer inside the second layer in the plan view. effective concentration of a second conductivity type impurity included in the second layer is higher than that of the first layer, and lower than that of the third layer.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate and a gate insulating film. The silicon carbide substrate includes a first impurity region, a second impurity region, a third impurity region, a fourth impurity region, a fifth impurity region, and a sixth impurity region. A first main surface of the silicon carbide substrate is provided with a trench defined by a side surface and a bottom portion. The sixth impurity region includes a first region which faces the bottom portion and a second region which faces a second main surface of the silicon carbide substrate. The first region is higher in impurity concentration than the second region. In a direction perpendicular to the second main surface, a fifth main surface of the fourth impurity region is located between a sixth main surface of the second impurity region and the second main surface.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate, a gate insulating film, and a gate electrode. The gate insulating film is provided as being in contact with the first main surface of the silicon carbide substrate. The gate electrode is provided on the gate insulating film such that the gate insulating film lies between the gate electrode and the silicon carbide substrate. In a first stress test in which a gate voltage of ?5 V is applied to the gate electrode for 100 hours at a temperature of 175° C., an absolute value of a difference between a first threshold voltage and a second threshold voltage is not more than 0.5 V, with a threshold voltage before the first stress test being defined as the first threshold voltage and a threshold voltage after the first stress test being defined as the second threshold voltage.

Abstract: A silicon carbide layer includes a drift region, a body region and a source region. The drift region constitutes a first main surface and has a first conductivity type. The body region is provided on the drift region, and has a second conductivity type. It is provided on the body region to be separated from the drift region, constitutes a second main surface, and has the first conductivity type. The silicon carbide layer is provided with a trench including a first side wall portion and a first bottom portion. The silicon carbide layer is embedded in the drift region to face the first bottom portion, and includes a second conductivity type region having the second conductivity type. The second conductivity type region is electrically connected to the source region.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate and a gate insulating film. The silicon carbide substrate includes a first impurity region, a second impurity region, a third impurity region, a fourth impurity region, a fifth impurity region, and a sixth impurity region. A first main surface of the silicon carbide substrate is provided with a trench defined by a side surface and a bottom portion. The sixth impurity region includes a first region which faces the bottom portion and a second region which faces a second main surface of the silicon carbide substrate. The first region is higher in impurity concentration than the second region. In a direction perpendicular to the second main surface, a fifth main surface of the fourth impurity region is located between a sixth main surface of the second impurity region and the second main surface.

Abstract: A silicon carbide film has first and second main surfaces. The second main surface has an element formation surface and a termination surface. The silicon carbide film has a first range that constitutes a first main surface and an intermediate surface opposite to the first main surface, and a second range that is provided on the intermediate surface and constitutes the element formation surface. The first range includes: a first breakdown voltage holding layer, and a guard ring region partially provided at the intermediate surface in the termination portion. The second range has a second breakdown voltage holding layer. The second range has one of a structure only having the second breakdown voltage holding layer in the termination portion and a structure disposed only in the element portion of the element portion and the termination portion.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate, a gate oxide film, and a gate electrode. A trench is provided in the main surface to have a side surface and a bottom portion. A contact point between a first side surface portion and a second side surface portion is located in a third impurity region. An angle formed by the first side surface portion and a straight line extending through the contact point and parallel to the main surface is smaller than an angle formed by the second side surface portion and a boundary surface between a first impurity region and a second impurity region. A thickness of a portion of the gate oxide film on the contact point between the main surface and the first side surface portion is larger than a thickness of a portion of the gate oxide film on the second impurity region.

Abstract: A silicon carbide layer includes a drift region, a body region and a source region. The drift region constitutes a first main surface and has a first conductivity type. The body region is provided on the drift region, and has a second conductivity type. It is provided on the body region to be separated from the drift region, constitutes a second main surface, and has the first conductivity type. The silicon carbide layer is provided with a trench including a first side wall portion and a first bottom portion. The silicon carbide layer is embedded in the drift region to face the first bottom portion, and includes a second conductivity type region having the second conductivity type. The second conductivity type region is electrically connected to the source region.

Abstract: A silicon carbide semiconductor substrate includes: a base substrate that has a main surface having an outer diameter of not less than 100 mm and that is made of single-crystal silicon carbide; and an epitaxial layer formed on the main surface. The silicon carbide semiconductor substrate has an amount of warpage of not less than ?100 ?m and not more than 100 ?m when a substrate temperature is a room temperature and has an amount of warpage of not less than ?1.5 mm and not more than 1.5 mm when the substrate temperature is 400° C.