Abstract: A silicon carbide semiconductor device includes: a silicon carbide semiconductor layer having a main surface, the main surface being provided with a trench which has a bottom portion and a sidewall inclined with respect to the main surface; a gate insulating film covering each of the bottom portion and the sidewall; a gate electrode provided at least on the gate insulating film; and an upper insulating film provided on the main surface and having a part which protrudes into the trench.

Abstract: A method for manufacturing a silicon carbide semiconductor device includes the following steps. A silicon carbide substrate is prepared. A first heating step of heating the silicon carbide substrate in an atmosphere of oxygen is performed. A second heating step of heating the silicon carbide substrate to a temperature of 1300° C. or more and 1500° C. or less in an atmosphere of gas containing nitrogen atoms or phosphorus atoms is performed after the first heating step. A third heating step of heating the silicon carbide substrate in an atmosphere of a first inert gas is performed after the second heating step. Thus, the silicon carbide semiconductor device in which threshold voltage variation is small, and a method for manufacturing the same can be provided.

Abstract: A method for manufacturing a SiC semiconductor device includes the steps of: forming an impurity region in a SiC layer; forming a first carbon layer on a surface of the SiC layer having the impurity region formed therein, by selectively removing silicon from the surface; forming a second carbon layer on the first carbon layer; and heating the SiC layer having the first carbon layer and the second carbon layer formed therein.

Abstract: A silicon carbide semiconductor device includes a silicon carbide semiconductor layer having a main surface, the main surface of the silicon carbide semiconductor layer being provided with a trench having a closed shape when seen in plan view, the trench including a bottom, a plurality of sidewalls continuous with the bottom, and a sidewall-connecting corner portion at a connection portion between two adjacent sidewalls of the plurality of sidewalls, the silicon carbide semiconductor device further including a gate insulating film covering the bottom and the sidewalls of the trench, and a gate electrode provided on the gate insulating film, between the bottom and an upper end of the trench, the thickness of the gate insulating film at the sidewall-connecting corner portion of the trench being greater than the thickness of the gate insulating film at a portion other than the sidewall-connecting corner portion.

Abstract: There is provided a silicon carbide semiconductor device allowing for integration of a transistor element and a Schottky barrier diode while avoiding reduction of an active region and decrease of a breakdown voltage. A silicon carbide semiconductor device includes a silicon carbide layer. The silicon carbide layer includes: a first region defining an outer circumference portion of an element region in which a transistor element is provided; and a JTE region provided external to the first region in a drift layer and electrically connected to the first region. The first region is provided with at least one opening through which the drift layer is exposed. The silicon carbide semiconductor device further includes a Schottky electrode provided in the opening and forming a Schottky junction with the drift layer.

Abstract: Provided is a silicon carbide semiconductor device that enables integration of a transistor element and a Schottky barrier diode while avoiding the reduction of an active region. A silicon carbide semiconductor device includes a silicon carbide layer, a gate insulating film, a Schottky electrode being Schottky functioned to a drift layer via a first contact hole and an opening, a gate electrode being arranged on the gate insulating film, an insulating layer being arranged so as to cover the gate insulating film, the gate electrode, and the Schottky electrode and having a second contact hole for exposing the gate electrode, and a gate pad electrode being arranged on the insulating layer so as to overlap the Schottky electrode in a plan view and being electrically connected to the gate electrode via the second contact hole.

Abstract: A silicon carbide semiconductor device includes a silicon carbide semiconductor layer, a gate insulating film formed on the silicon carbide semiconductor layer, and a gate electrode provided on the gate insulating film, wherein the gate electrode has a polysilicon layer at least on a side of an interface with the gate insulating film, and the gate insulating film has an oxide film derived from the polysilicon layer, at an interface between the gate insulating film and the polysilicon layer of the gate electrode.

Abstract: The silicon carbide semiconductor layer includes a first impurity region, a second impurity region, and a third impurity region. Turning to a first position at which an impurity concentration 1/10 as high as a highest impurity concentration is exhibited in a concentration profile of an impurity having the first conductivity type in a direction perpendicular to the main surface in the third impurity region and a second position at which an impurity concentration 1/10 as high as a highest impurity concentration is exhibited in a concentration profile of an impurity having the second conductivity type in the direction perpendicular to the main surface in the second impurity region, a first depth from the main surface to the first position is shallower than a second depth from the main surface to the second position. The electrode is electrically connected to the second impurity region and the third impurity region.

Abstract: A SiC semiconductor device includes a SiC substrate, a gate insulating film formed on a surface of the SiC substrate and made of SiO2, and a gate electrode formed on the gate insulating film. A maximum value of a nitrogen concentration in a region within 10 nm from an interface between the SiC substrate and the gate insulating film is greater than or equal to 3×1019 cm?3. A maximum value of a nitrogen concentration in a region within 10 nm from an interface between the gate insulating film and the gate electrode is less than or equal to 1×1020 cm?3.

Abstract: A silicon carbide semiconductor device capable of achieving a high current gain with a simplified construction is provided. A silicon carbide layer includes a collector region, a base region, and an emitter region. The silicon carbide layer is provided with a trench having a sidewall surface reaching the base region from a first main surface through the emitter region. The sidewall surface includes a region macroscopically having an angle not smaller than 50° and not greater than 70° with respect to a {000-1} plane. A manufacturing method includes the step of forming a trench. The step of forming a trench includes the step of chemically treating the first main surface of the silicon carbide layer for forming the region.

Abstract: A method for manufacturing a silicon carbide semiconductor device includes steps of preparing a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, forming a groove portion in the first main surface of the silicon carbide substrate, and cutting the silicon carbide substrate at the groove portion. The step of forming the groove portion includes a step of thermally etching the silicon carbide substrate using chlorine. Thereby, a method for manufacturing a silicon carbide semiconductor device capable of suppressing damage to a chip is provided.

Abstract: A silicon carbide semiconductor device includes: a silicon carbide off substrate including a main surface having an off angle relative to a basal plane, the main surface being provided with a trench, the trench having a plurality of side walls and a bottom portion; a gate insulating film covering the side walls and the bottom portion; and a gate electrode provided on the gate insulating film, each of the side walls having an angle of more than 65° and not more than 80° relative to the basal plane in the trench, opening directions of the plurality of side walls being all at a silicon plane side or a carbon plane side.

Abstract: A silicon carbide semiconductor substrate includes: a base substrate that has a main surface having an outer diameter of not less than 100 mm and that is made of single-crystal silicon carbide; and an epitaxial layer formed on the main surface, a groove being formed in a main surface of the epitaxial layer or a backside surface of the base substrate opposite to the main surface of the base substrate. In this way, the groove suppresses the substrate from being deformed (warped during a high temperature treatment, for example). This can reduce a risk of causing defects such as crack in the silicon carbide semiconductor substrate during the manufacturing process in performing a method for manufacturing a silicon carbide semiconductor device using the silicon carbide semiconductor substrate.

Abstract: A silicon carbide semiconductor substrate includes: a base substrate that has a main surface having an outer diameter of not less than 100 mm and that is made of single-crystal silicon carbide; and an epitaxial layer formed on the main surface. The silicon carbide semiconductor substrate has an amount of warpage of not less than ?100 ?m and not more than 100 ?m when a substrate temperature is a room temperature and has an amount of warpage of not less than ?1.5 mm and not more than 1.5 mm when the substrate temperature is 400° C.

Abstract: A silicon carbide layer includes a drift region, a body region and a source region. The drift region constitutes a first main surface and has a first conductivity type. The body region is provided on the drift region, and has a second conductivity type. It is provided on the body region to be separated from the drift region, constitutes a second main surface, and has the first conductivity type. The silicon carbide layer is provided with a trench including a first side wall portion and a first bottom portion. The silicon carbide layer is embedded in the drift region to face the first bottom portion, and includes a second conductivity type region having the second conductivity type. The second conductivity type region is electrically connected to the source region.

Abstract: A semiconductor substrate having a main surface and made of a wide band gap semiconductor is provided, the semiconductor substrate including a device region formed in the semiconductor substrate, and a peripheral region formed to surround the device region. In the peripheral region, the semiconductor substrate includes a first semiconductor region having a first conductivity type, and a second semiconductor region formed on the first semiconductor region and having the main surface, the second semiconductor region having a second conductivity type different from the first conductivity type. At an outermost periphery of the peripheral region, the semiconductor substrate has a plurality of stepped portions annularly surrounding the device region, and the second semiconductor region is formed along the stepped portion.

Abstract: A silicon carbide semiconductor device includes a silicon carbide layer and a gate insulating layer. The silicon carbide layer has a main surface. The gate insulating layer is arranged as being in contact with the main surface of the silicon carbide layer. The silicon carbide layer includes a drift region having a first conductivity type, a body region having a second conductivity type different from the first conductivity type and being in contact with the drift region, a source region having the first conductivity type and arranged as being spaced apart from the drift region by the body region, and a protruding region arranged to protrude from at least one side of the source region and the drift region into the body region, being in contact with the gate insulating layer, and having the first conductivity type.

Abstract: A semiconductor substrate (epitaxial substrate) having a main surface (upper surface) and made of a wide band gap semiconductor is provided, the semiconductor substrate including a device region formed in the semiconductor substrate, and a peripheral region formed to surround the device region. In the peripheral region, the semiconductor substrate includes a first semiconductor region (drift layer) having a first conductivity type, and a second semiconductor region (electric field relaxing region) formed on the first semiconductor region (drift layer) and having the main surface, the second semiconductor region having a second conductivity type different from the first conductivity type, and a plurality of trenches annularly surrounding the device region are formed in the main surface of the second semiconductor region (electric field relaxing region). Consequently, a wide band gap semiconductor device capable of achieving a higher breakdown voltage is provided without an increase in size.

Abstract: A silicon carbide semiconductor substrate includes: a base substrate that has a main surface having an outer diameter of not less than 100 mm and that is made of single-crystal silicon carbide; an epitaxial layer formed on the main surface; and a deformation suppression layer formed on a backside surface of the base substrate opposite to the main surface. In this way, the deformation suppression layer suppresses the substrate from being deformed (for example, warped during high-temperature treatment). This can reduce a risk of causing defects such as crack in the silicon carbide semiconductor substrate during the manufacturing process in performing a method for manufacturing a silicon carbide semiconductor device using the silicon carbide semiconductor substrate.

Abstract: The steps of preparing a silicon carbide layer having a main surface, forming on the main surface, a first mask layer located on a first region to be a channel region and having a first opening portion on each of opposing regions with the first region lying therebetween, and forming a high-concentration impurity region having a first conductivity type and being higher in impurity concentration than the silicon carbide layer in a region exposed through the first opening portion, by implanting ions into the main surface with the first mask layer being interposed are included.