Patents by Inventor Takeyoshi Nishimura

Takeyoshi Nishimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12720799
    Abstract: A semiconductor device, including: a semiconductor substrate, a drift layer provided on the semiconductor substrate, a base layer provided in the drift layer at a surface thereof, a plurality of source regions selectively provided in the base layer at a surface thereof, a plurality of gate electrodes provided in the base layer and the source regions via a plurality of gate insulating films, respectively, an interlayer insulating film covering the source regions and the gate electrodes, a plurality of contact holes provided in the interlayer insulating film and in the source regions at the surfaces thereof, and a front electrode provided on the interlayer insulating film. A longitudinal direction of each contact hole is a first direction. The front electrode includes an upper electrode provided on a lower electrode, the upper electrode having a plurality of recesses formed therein each extending in a second direction orthogonal to the first direction.
    Type: Grant
    Filed: February 26, 2024
    Date of Patent: August 25, 2026
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Takeyoshi Nishimura
  • Patent number: 12414316
    Abstract: A method of manufacturing a silicon carbide semiconductor device includes selectively forming a semiconductor region of a conductivity type at a first main surface of a semiconductor substrate containing silicon carbide; forming a nickel layer above the semiconductor region; ion-implanting aluminum in the nickel layer; performing a heat treatment to the nickel layer implanted with the aluminum to thereby form an ohmic contact layer in ohmic contact with the semiconductor region; forming a first electrode that is in contact with the ohmic contact layer, the semiconductor region, and the semiconductor substrate; and forming a second electrode on a second main surface of the semiconductor substrate.
    Type: Grant
    Filed: September 22, 2022
    Date of Patent: September 9, 2025
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Takeyoshi Nishimura
  • Publication number: 20250159926
    Abstract: A semiconductor device including an active area and a voltage blocking area provided outwardly from the active area, the semiconductor device including: a semiconductor layer having a first conductivity type and provided over the active area and the voltage blocking area; a semiconductor region having a second conductivity type and provided on a top surface side of the semiconductor layer, in an edge section on the voltage blocking area side of the active area; and a contact section provided on a top surface side of the semiconductor region, wherein the contact section includes: a first stripe portion extending in a first direction along the edge section on the voltage blocking area side of the active area in a plan view; and a plurality of first connecting portions connected to the first stripe portion and separated from each other in the first direction.
    Type: Application
    Filed: September 27, 2024
    Publication date: May 15, 2025
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Takeyoshi NISHIMURA
  • Publication number: 20250095996
    Abstract: A front electrode is in ohmic contact with a semiconductor substrate via a contact structure having a TiSix film, a TiN film, and a metal plug. The TiSix film is deposited directly by sputtering, and is provided along sidewalls (side surfaces of an interlayer insulating film) of a contact hole to an inner wall of a source contact trench. Ends of the TiSix film terminate on the side surfaces of the interlayer insulating film. A thickness of the TiSix film is uniform from the sidewalls of the contact hole to sidewalls of the source contact trench. The TiN film is provided along a surface of the TiSix film. The metal plug is embedded in the contact hole and the source contact trench, onto the TiN film.
    Type: Application
    Filed: November 27, 2024
    Publication date: March 20, 2025
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Takeyoshi NISHIMURA
  • Publication number: 20240371993
    Abstract: A semiconductor device, including: a semiconductor substrate, a drift layer provided on the semiconductor substrate, a base layer provided in the drift layer at a surface thereof, a plurality of source regions selectively provided in the base layer at a surface thereof, a plurality of gate electrodes provided in the base layer and the source regions via a plurality of gate insulating films, respectively, an interlayer insulating film covering the source regions and the gate electrodes, a plurality of contact holes provided in the interlayer insulating film and in the source regions at the surfaces thereof, and a front electrode provided on the interlayer insulating film. A longitudinal direction of each contact hole is a first direction. The front electrode includes an upper electrode provided on a lower electrode, the upper electrode having a plurality of recesses formed therein each extending in a second direction orthogonal to the first direction.
    Type: Application
    Filed: February 26, 2024
    Publication date: November 7, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Takeyoshi NISHIMURA
  • Patent number: 11699727
    Abstract: Provided is a semiconductor device including: a drift region of first conductivity type provided in a semiconductor substrate; a base region of second conductivity type provided in the semiconductor substrate; an emitter region of first conductivity type provided at a front surface of the semiconductor substrate; a contact region of second conductivity type provided on the base region and having a higher doping concentration than the base region; a contact trench portion provided at the front surface of the semiconductor substrate; a first barrier layer provided at a side wall and a bottom surface of the contact trench portion; and a second barrier layer provided in contact with the contact region at the side wall of the contact trench portion.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: July 11, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Makoto Shimosawa, Takeyoshi Nishimura
  • Publication number: 20230143787
    Abstract: A semiconductor device includes a temperature sensing unit including a plurality of temperature sensing diode portions each including an anode portion provided above a front surface of a semiconductor substrate and a cathode portion coupled to the anode portion and connected in series and a resistance portion of an N type electrically connected to the temperature sensing diode portion. A sum of resistance values of the cathode portion and the resistance portion is greater than a resistance value of the anode portion.
    Type: Application
    Filed: September 25, 2022
    Publication date: May 11, 2023
    Inventor: Takeyoshi NISHIMURA
  • Patent number: 11600722
    Abstract: Provided are a semiconductor element and a semiconductor device capable of achieving on-resistance reduction and miniaturization. The semiconductor element is used in a semiconductor switch for protecting an electric circuit, and includes a semiconductor substrate SB, a MOS transistor Tr provided on the semiconductor substrate SB, and a source electrode SE provided on a front surface 2a side of the semiconductor substrate SB. The MOS transistor Tr includes an n-type source region 8 connected to the source electrode SE, an n-type drift region 21 arranged away from the source region 8, and a p-type well region 31 arranged between the source region 8 and the drift region 21. The source region 8 is interposed between the source electrode SE and the well region 31.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: March 7, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Takeyoshi Nishimura
  • Patent number: 11545460
    Abstract: A semiconductor device includes a semiconductor element having a surface electrode layer; a first wire that is electrically connected to the first main surface of the surface electrode layer at a plurality of first connecting portions and is arranged in a first direction on the first main surface; and a second wire that is electrically connected to the first main surface of the surface electrode layer at a second connecting portion and is arranged in a second direction on the first main surface, wherein a second circle equivalent diameter, which is a diameter of a circle having a same cross-sectional area as the second wire, is larger than a first circle equivalent diameter, which is a diameter of a circle having a same cross-sectional area as the first wire.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: January 3, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Takeyoshi Nishimura
  • Patent number: 11469318
    Abstract: A semiconductor device has an active region through which current passes and an edge termination structure region. On a front surface of a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type is provided. On a surface of the first semiconductor layer, a parallel pn structure including first columns of the first conductivity type and second columns of a second conductivity type disposed to repeatedly alternate one another is provided. The second columns in the active region include first regions and second regions. A distance from the front surface of the semiconductor substrate to a bottom surface of one of the first regions is greater than a distance from the front surface of the semiconductor substrate to a bottom surface of one of the second regions.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: October 11, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takeyoshi Nishimura, Ryo Maeta, Isamu Sugai
  • Patent number: 11394881
    Abstract: An image processing apparatus includes processing circuitry. The processing circuitry is configured to detect a positional shift amount of each of a plurality of images; select a composite target image from the plurality of images based on the detected positional shift amount; and obtain a composite image based on the positional shift amount and the selected composite target image.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: July 19, 2022
    Assignee: RICOH COMPANY, LTD.
    Inventors: Hiroyasu Uehara, Masakazu Terauchi, Masashi Miyata, Hiroshi Kano, Akira Nakano, Takeyoshi Nishimura
  • Patent number: 11322582
    Abstract: A semiconductor device, including a parallel pn layer formed on a semiconductor substrate, and an insulated gate structure provided on the parallel pn layer. The parallel pn layer includes a plurality of first regions and a plurality of second regions disposed repeatedly alternating one another along a first direction that is parallel to an upper surface of the semiconductor substrate. Each of the first regions and second regions has, along the first direction, an impurity concentration that has a maximum value thereof at a peak position and that decreases gradually from the peak position. Each of the first regions and second regions has, along a depth direction thereof, a first part and a second part, a gradient of the impurity concentration along the first direction being respectively symmetrical and asymmetrical in the first part and in the second part, with respect to the peak position.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: May 3, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Takeyoshi Nishimura
  • Patent number: 11282946
    Abstract: A semiconductor device includes an enhancement mode MOSFET and a junction FET. The MOSFET has a first semiconductor substrate of a first conductivity type, a first first-semiconductor-layer of the first conductivity type, first second-semiconductor-regions of a second conductivity type, first first-semiconductor-regions of the first conductivity type, first gate insulating films, first gate electrodes, a first first-electrode, and a first second-electrode. The FET has a second semiconductor substrate of the first conductivity type, a second first-semiconductor-layer of the first conductivity type, second first-semiconductor-regions of the first conductivity type, a second second-semiconductor-layer of the second conductivity type, second gate electrodes, a second first-electrode, and a second second-electrode. The first second-electrode and the second second-electrode are connected electrically.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: March 22, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Takeyoshi Nishimura
  • Publication number: 20220013645
    Abstract: Provided is a semiconductor device including: a drift region of first conductivity type provided in a semiconductor substrate; a base region of second conductivity type provided in the semiconductor substrate; an emitter region of first conductivity type provided at a front surface of the semiconductor substrate; a contact region of second conductivity type provided on the base region and having a higher doping concentration than the base region; a contact trench portion provided at the front surface of the semiconductor substrate; a first barrier layer provided at a side wall and a bottom surface of the contact trench portion; and a second barrier layer provided in contact with the contact region at the side wall of the contact trench portion.
    Type: Application
    Filed: May 25, 2021
    Publication date: January 13, 2022
    Inventors: Makoto SHIMOSAWA, Takeyoshi NISHIMURA
  • Publication number: 20210375855
    Abstract: A semiconductor device includes an enhancement mode MOSFET and a junction FET. The MOSFET has a first semiconductor substrate of a first conductivity type, a first first-semiconductor-layer of the first conductivity type, first second-semiconductor-regions of a second conductivity type, first first-semiconductor-regions of the first conductivity type, first gate insulating films, first gate electrodes, a first first-electrode, and a first second-electrode. The FET has a second semiconductor substrate of the first conductivity type, a second first-semiconductor-layer of the first conductivity type, second first-semiconductor-regions of the first conductivity type, a second second-semiconductor-layer of the second conductivity type, second gate electrodes, a second first-electrode, and a second second-electrode. The first second-electrode and the second second-electrode are connected electrically.
    Type: Application
    Filed: March 31, 2021
    Publication date: December 2, 2021
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Takeyoshi NISHIMURA
  • Publication number: 20210320171
    Abstract: A method of manufacturing a superjunction device, including forming a first semiconductor layer of a first conductivity type on a semiconductor substrate, forming a plurality of first trenches from the first semiconductor layer, forming a second semiconductor layer of the first conductivity type on the first semiconductor layer and in the first trenches, implanting an impurity of a second conductivity type in the second semiconductor layer, thereby forming a plurality of well regions of the second conductivity type, and a parallel pn structure including first and second columns alternating one another repeatedly in a direction parallel to a surface of the semiconductor substrate, forming a plurality of second trenches penetrating through the second semiconductor layer and reaching the first columns, forming a plurality of second semiconductor regions of the second conductivity type in the well regions in the active region, and selectively forming a plurality of first semiconductor regions of the first conduct
    Type: Application
    Filed: February 26, 2021
    Publication date: October 14, 2021
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Takeyoshi NISHIMURA
  • Publication number: 20210217723
    Abstract: A semiconductor device includes a semiconductor element having a surface electrode layer; a first wire that is electrically connected to the first main surface of the surface electrode layer at a plurality of first connecting portions and is arranged in a first direction on the first main surface; and a second wire that is electrically connected to the first main surface of the surface electrode layer at a second connecting portion and is arranged in a second direction on the first main surface, wherein a second circle equivalent diameter, which is a diameter of a circle having a same cross-sectional area as the second wire, is larger than a first circle equivalent diameter, which is a diameter of a circle having a same cross-sectional area as the first wire.
    Type: Application
    Filed: December 1, 2020
    Publication date: July 15, 2021
    Applicant: Fuji Electric Co., Ltd.
    Inventor: Takeyoshi NISHIMURA
  • Patent number: 11012633
    Abstract: An image capturing apparatus includes an image data acquirer configured to acquire pieces of image data at a plurality of relative movement positions to which an imaging surface of an imaging sensor is relatively moved with respect to an object light flux; an exposure changer configured to change an exposure when acquiring the pieces of image data at the plurality of relative movement positions; a dynamic range adjuster configured to adjust a dynamic range of the acquired pieces of image data; and an image data combiner configured to obtain composite image data of the pieces of image data, based on a positional shift amount between the pieces of image data and the dynamic range.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: May 18, 2021
    Assignee: Ricoh Company, Ltd.
    Inventors: Masakazu Terauchi, Hiroyasu Uehara, Masashi Miyata, Hiroshi Kano, Takeyoshi Nishimura
  • Publication number: 20210074808
    Abstract: A semiconductor device, including a parallel pn layer formed on a semiconductor substrate, and an insulated gate structure provided on the parallel pn layer. The parallel pn layer includes a plurality of first regions and a plurality of second regions disposed repeatedly alternating one another along a first direction that is parallel to an upper surface of the semiconductor substrate. Each of the first regions and second regions has, along the first direction, an impurity concentration that has a maximum value thereof at a peak position and that decreases gradually from the peak position. Each of the first regions and second regions has, along a depth direction thereof, a first part and a second part, a gradient of the impurity concentration along the first direction being respectively symmetrical and asymmetrical in the first part and in the second part, with respect to the peak position.
    Type: Application
    Filed: August 3, 2020
    Publication date: March 11, 2021
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Takeyoshi NISHIMURA
  • Patent number: 10943997
    Abstract: A semiconductor layer may be subjected to etching to form a trench therein. An epitaxial layer may be further formed in the trench. Here, the impurity concentration of the epitaxial layer is controlled to be lower than that of the semiconductor layer. In this manner, concentration of electrical fields in the trench is reduced. A first innovations herein provides a semiconductor device including a first semiconductor layer containing impurities of a first conductivity type, a trench provided in the first semiconductor layer on a front surface side thereof, and a second semiconductor layer provided on an inner wall of the trench, where the second semiconductor layer contains impurities of the first conductivity type at a lower concentration than the first semiconductor layer.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: March 9, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Takeyoshi Nishimura