Patents by Inventor Takeyoshi Nishimura

Takeyoshi Nishimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200365719
    Abstract: A semiconductor device has an active region through which current passes and an edge termination structure region. On a front surface of a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type is provided. On a surface of the first semiconductor layer, a parallel pn structure including first columns of the first conductivity type and second columns of a second conductivity type disposed to repeatedly alternate one another is provided. The second columns in the active region include first regions and second regions. A distance from the front surface of the semiconductor substrate to a bottom surface of one of the first regions is greater than a distance from the front surface of the semiconductor substrate to a bottom surface of one of the second regions.
    Type: Application
    Filed: March 31, 2020
    Publication date: November 19, 2020
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Takeyoshi NISHIMURA, Ryo MAETA, Isamu SUGAI
  • Publication number: 20200358952
    Abstract: An image processing apparatus includes processing circuitry. The processing circuitry is configured to detect a positional shift amount of each of a plurality of images; select a composite target image from the plurality of images based on the detected positional shift amount; and obtain a composite image based on the positional shift amount and the selected composite target image.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Inventors: Hiroyasu UEHARA, Masakazu TERAUCHI, Masashi MIYATA, Hiroshi KANO, Akira NAKANO, Takeyoshi NISHIMURA
  • Patent number: 10764495
    Abstract: An image processing apparatus includes processing circuitry. The processing circuitry is configured to detect a positional shift amount of each of a plurality of images; select a composite target image from the plurality of images based on the detected positional shift amount; and obtain a composite image based on the positional shift amount and the selected composite target image.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: September 1, 2020
    Assignee: Ricoh Company, Ltd.
    Inventors: Hiroyasu Uehara, Masakazu Terauchi, Masashi Miyata, Hiroshi Kano, Akira Nakano, Takeyoshi Nishimura
  • Publication number: 20200203515
    Abstract: A semiconductor layer may be subjected to etching to form a trench therein. An epitaxial layer may be further formed in the trench. Here, the impurity concentration of the epitaxial layer is controlled to be lower than that of the semiconductor layer. In this manner, concentration of electrical fields in the trench is reduced. A first innovations herein provides a semiconductor device including a first semiconductor layer containing impurities of a first conductivity type, a trench provided in the first semiconductor layer on a front surface side thereof, and a second semiconductor layer provided on an inner wall of the trench, where the second semiconductor layer contains impurities of the first conductivity type at a lower concentration than the first semiconductor layer.
    Type: Application
    Filed: March 4, 2020
    Publication date: June 25, 2020
    Inventor: Takeyoshi NISHIMURA
  • Patent number: 10692751
    Abstract: In each n-type epitaxial layer, p-type impurity regions are respectively formed by performing for each stacking of an n-type epitaxial layer, ion implantation using a resist mask. In a first n-type epitaxial layer, a p-type impurity region is formed at an inner wall of an impurity diffusion trench formed by dry etching. In a second and third n-type epitaxial layer, p-type impurity regions are formed respectively at an inner wall of impurity diffusion trenches that are recesses respectively corresponding to the impurity diffusion trenches of the first and the second n-type epitaxial layers respectively therebelow. The resist mask has an opening width that is wider than widths of open ends of the impurity diffusion trenches. The p-type impurity regions are connected by thermal diffusion processing, thereby forming a parallel pn layer constituted by p-type regions having a high aspect ratio and n-type regions respectively between the p-type regions.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: June 23, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Toshiaki Sakata, Takeyoshi Nishimura, Isamu Sugai, Kazuya Yamaguchi
  • Patent number: 10673425
    Abstract: A current limiting resistor opposes a p-type anode region of a bootstrap diode in a depth direction, across an insulating film. The current limiting resistor is configured by poly-silicon layers constituting poly-silicon resistors, and a poly-silicon connector that is a connector connected to a limiting resistor electrode. The poly-silicon layers are disposed further outside than is the poly-silicon connector and each has a first end connected to the poly-silicon connector. The poly-silicon layers each have a second end and a part that is toward the second end and that is in contact with an anode electrode via a contact hole. Further, the poly-silicon layers are disposed evenly between a part thereof connected to the poly-silicon connector and the contact hole.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: June 2, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Takeyoshi Nishimura
  • Publication number: 20200105923
    Abstract: Provided are a semiconductor element and a semiconductor device capable of achieving on-resistance reduction and miniaturization. The semiconductor element is used in a semiconductor switch for protecting an electric circuit, and includes a semiconductor substrate SB, a MOS transistor Tr provided on the semiconductor substrate SB, and a source electrode SE provided on a front surface 2a side of the semiconductor substrate SB. The MOS transistor Tr includes an n-type source region 8 connected to the source electrode SE, an n-type drift region 21 arranged away from the source region 8, and a p-type well region 31 arranged between the source region 8 and the drift region 21. The source region 8 is interposed between the source electrode SE and the well region 31.
    Type: Application
    Filed: August 23, 2019
    Publication date: April 2, 2020
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Takeyoshi Nishimura
  • Publication number: 20200091135
    Abstract: Provided are a semiconductor element and a semiconductor device capable of reducing possibilities of malfunctions and breakdowns due to temperature rise. A semiconductor element (50) includes a first MOS transistor (Tr1), a second MOS transistor (Tr2), and a temperature detecting element (TD) that are provided on a semiconductor substrate (SB). The first MOS transistor (Tr1) includes an n-type source region (8), an n-type first semiconductor region (21) arranged away from the source region (8) and a p-type well region (31) arranged between the source region (8) and the first semiconductor region (21). The second MOS transistor (Tr2) includes an n-type source region (8) an n-type second semiconductor region (22) arranged away from the source region (8), and a p-type well region (31) arranged between the source region (8) and the second semiconductor region (22). The first semiconductor region (21) is connected to the second semiconductor region (22).
    Type: Application
    Filed: July 24, 2019
    Publication date: March 19, 2020
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Takeyoshi NISHIMURA, Isamu SUGAI
  • Patent number: 10593787
    Abstract: A semiconductor layer may be subjected to etching to form a trench therein. An epitaxial layer may be further formed in the trench. Here, the impurity concentration of the epitaxial layer is controlled to be lower than that of the semiconductor layer. In this manner, concentration of electrical fields in the trench is reduced. A first innovations herein provides a semiconductor device including a first semiconductor layer containing impurities of a first conductivity type, a trench provided in the first semiconductor layer on a front surface side thereof, and a second semiconductor layer provided on an inner wall of the trench, where the second semiconductor layer contains impurities of the first conductivity type at a lower concentration than the first semiconductor layer.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: March 17, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Takeyoshi Nishimura
  • Patent number: 10484607
    Abstract: A shake correction control device includes circuitry to control an ON/OFF timing of horizontal synchronizing signals of an image capture element, and an ON/OFF timing of one or more drive signals used for correcting a shake of the image capture element, shift at least one of the ON/OFF timing of the drive signals used for correcting the shake of the image capture element so as to be out of a period of time during which analog/digital (A/D) conversion processing is collectively performed on pixel signals for one or more horizontal lines of the image capture element, and adjust the at least one of the ON/OFF timing of the drive signals used for correcting the shake of the image capture element with respect to the horizontal synchronizing signals based on the number of the one or more horizontal lines of the pixel signals collectively subjected to the A/D conversion processing.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: November 19, 2019
    Assignee: Ricoh Company, Ltd.
    Inventors: Takeyoshi Nishimura, Naoto Asakura
  • Publication number: 20190348318
    Abstract: In each n-type epitaxial layer, p-type impurity regions are respectively formed by performing for each stacking of an n-type epitaxial layer, ion implantation using a resist mask. In a first n-type epitaxial layer, a p-type impurity region is formed at an inner wall of an impurity diffusion trench formed by dry etching. In a second and third n-type epitaxial layer, p-type impurity regions are formed respectively at an inner wall of impurity diffusion trenches that are recesses respectively corresponding to the impurity diffusion trenches of the first and the second n-type epitaxial layers respectively therebelow. The resist mask has an opening width that is wider than widths of open ends of the impurity diffusion trenches. The p-type impurity regions are connected by thermal diffusion processing, thereby forming a parallel pn layer constituted by p-type regions having a high aspect ratio and n-type regions respectively between the p-type regions.
    Type: Application
    Filed: March 27, 2019
    Publication date: November 14, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Toshiaki SAKATA, Takeyoshi NISHIMURA, Isamu SUGAI, Kazuya YAMAGUCHI
  • Patent number: 10465684
    Abstract: A rotary compressor includes a cylinder having a cylinder chamber and bush groove, a piston housed in the cylinder chamber, a blade formed with the piston to separate the cylinder chamber into low and high pressure chambers, and a pair of bushes. The bushes are fitted in the bush groove with flat surfaces facing each other to hold the blade. The flat surface of at least the bush on the low-pressure side has a crowned portion starting from a position closer to the back pressure space than a swing center position, and extending toward an edge of the bush closer to the cylinder chamber. The swing center position is where a gap between the blade and the bush is constant while the piston rotates eccentrically.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: November 5, 2019
    Assignee: Daikin Industries, Ltd.
    Inventors: Kousuke Nishimura, Takeyoshi Ohkawa, Eiji Kumakura
  • Publication number: 20190334515
    Abstract: A current limiting resistor opposes a p-type anode region of a bootstrap diode in a depth direction, across an insulating film. The current limiting resistor is configured by poly-silicon layers constituting poly-silicon resistors, and a poly-silicon connector that is a connector connected to a limiting resistor electrode. The poly-silicon layers are disposed further outside than is the poly-silicon connector and each has a first end connected to the poly-silicon connector. The poly-silicon layers each have a second end and a part that is toward the second end and that is in contact with an anode electrode via a contact hole. Further, the poly-silicon layers are disposed evenly between a part thereof connected to the poly-silicon connector and the contact hole.
    Type: Application
    Filed: February 28, 2019
    Publication date: October 31, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Takeyoshi NISHIMURA
  • Patent number: 10453917
    Abstract: An n-type region and a p-type region of a first parallel pn layer are arranged parallel to a base front surface, in a striped planar layout extending from an active region over an edge termination region. In the n-type region, a gate trench extending linearly along a first direction is provided. In an intermediate region, in a surface region on the base front surface side of the first parallel pn layer, a second parallel pn layer is provided. The second parallel pn layer is arranged having a repetition cycle shifted along a second direction ½ a cell with respect to a repetition cycle of the n-type region and the p-type region of the first parallel pn layer. A gate trench termination portion terminates in the intermediate region between the active region and the edge termination region, and is covered by the p-type region of the second parallel pn layer.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: October 22, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Isamu Sugai, Takeyoshi Nishimura
  • Patent number: 10439061
    Abstract: A front surface electrode common to a plurality of unit cells is provided substantially all over an active region of a semiconductor element. A plurality of electrode pads on the front surface electrode are closer to the outer peripheral portion side than the central portion of the active region. Different wires are joined to substantially the center of each electrode pad. The active region is divided into two or more segments so that the segments are aligned along the path of current flowing through the front surface electrode, and unit cells different in conduction ability are disposed respectively in each segment. Unit cells lowest in conduction ability are in the first segment farthest from junctions of the wires and electrode pads, and the unit cells are disposed so that the farther apart from the junctions of the wires and electrode pads, the lower in conduction ability the unit cells are.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: October 8, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Takeyoshi Nishimura
  • Publication number: 20190297242
    Abstract: An image capturing apparatus includes an image data acquirer configured to acquire pieces of image data at a plurality of relative movement positions to which an imaging surface of an imaging sensor is relatively moved with respect to an object light flux; an exposure changer configured to change an exposure when acquiring the pieces of image data at the plurality of relative movement positions; a dynamic range adjuster configured to adjust a dynamic range of the acquired pieces of image data; and an image data combiner configured to obtain composite image data of the pieces of image data, based on a positional shift amount between the pieces of image data and the dynamic range.
    Type: Application
    Filed: March 20, 2019
    Publication date: September 26, 2019
    Applicant: Ricoh Company, Ltd.
    Inventors: Masakazu TERAUCHI, Hiroyasu UEHARA, Masashi MIYATA, Hiroshi KANO, Takeyoshi NISHIMURA
  • Patent number: 10396065
    Abstract: A capacitive component region is formed below a temperature detecting diode or below a protective diode. In addition, the capacitive component region is formed below an anode metal wiring line connecting the temperature detecting diode and an anode electrode pad and below a cathode metal wiring line connecting the temperature detecting diode and a cathode electrode pad. The capacitive component region is an insulating film interposed between polysilicon layers. Specifically, a first insulating film, a polysilicon conductive layer, and a second insulating film are sequentially formed on a first main surface of a semiconductor substrate, and the temperature detecting diode, the protective diode, the anode metal wiring line, or the cathode metal wiring line is formed on the upper surface of the second insulating film. Therefore, it is possible to improve the static electricity resistance of the temperature detecting diode or the protective diode.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: August 27, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Takeyoshi Nishimura
  • Patent number: 10381436
    Abstract: To provide a semiconductor device having a structure capable of forming a superjunction with less thermal history, a semiconductor device is provided, the semiconductor device including a contact trench formed between two gate trenches, penetrating through a source region, and including its lower end arranged in a base region, and a second conductivity-type protruding portion formed protruding toward a lower side from the lower end of the base region in a region opposite to the lower end of the contact trench, wherein the depth from the upper end of the source region to a lower end of the protruding portion is 3 ?m or more, and a carrier concentration Nd in a first conductivity-type region adjacent to the protruding portion in a lateral direction perpendicular to a depth direction and a carrier concentration Na of the protruding portion satisfy a predetermined equation.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: August 13, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Isamu Sugai, Takeyoshi Nishimura
  • Publication number: 20190191082
    Abstract: An image processing apparatus includes processing circuitry. The processing circuitry is configured to detect a positional shift amount of each of a plurality of images; select a composite target image from the plurality of images based on the detected positional shift amount; and obtain a composite image based on the positional shift amount and the selected composite target image.
    Type: Application
    Filed: December 12, 2018
    Publication date: June 20, 2019
    Inventors: Hiroyasu Uehara, Masakazu Terauchi, Masashi Miyata, Hiroshi Kano, Akira Nakano, Takeyoshi Nishimura
  • Publication number: 20190165092
    Abstract: An n-type region and a p-type region of a first parallel pn layer are arranged parallel to a base front surface, in a striped planar layout extending from an active region over an edge termination region. In the n-type region, a gate trench extending linearly along a first direction is provided. In an intermediate region, in a surface region on the base front surface side of the first parallel pn layer, a second parallel pn layer is provided. The second parallel pn layer is arranged having a repetition cycle shifted along a second direction ½ a cell with respect to a repetition cycle of the n-type region and the p-type region of the first parallel pn layer. A gate trench termination portion terminates in the intermediate region between the active region and the edge termination region, and is covered by the p-type region of the second parallel pn layer.
    Type: Application
    Filed: January 31, 2019
    Publication date: May 30, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Isamu SUGAI, Takeyoshi NISHIMURA