Abstract: A method of manufacturing a semiconductor device includes preparing a layer, including columns, the columns extend a first direction parallel to the surface of the layer, the columns are arranged at intervals, interdigitally sandwiching other columns so as to implement a superjunction structure so the columns and the other columns are side by side; forming well regions in the layer; forming source regions in the well regions; forming an insulating film on the well regions; and forming gate electrodes on the gate insulating film, the gate electrodes bridging corresponding source regions in neighboring well regions, a temperature detection diode at an area in the gate electrodes, one column has a first width in a second direction, the temperature detection diode has a second width in the second direction, and the first width equal to the second width, and the second direction is perpendicular to the first direction.

Abstract: A method of manufacturing a semiconductor device includes preparing a layer, including columns, the columns extend a first direction parallel to the surface of the layer, the columns are arranged at intervals, interdigitally sandwiching other columns so as to implement a superjunction structure so the columns and the other columns are side by side; forming well regions in the layer; forming source regions in the well regions; forming an insulating film on the well regions; and forming gate electrodes on the gate insulating film, the gate electrodes bridging corresponding source regions in neighboring well regions, a temperature detection diode at an area in the gate electrodes, one column has a first width in a second direction, the temperature detection diode has a second width in the second direction, and the first width equal to the second width, and the second direction is perpendicular to the first direction.

Abstract: A semiconductor device includes a drift layer of a first conductivity-type, having a super junction structure, including a plurality of columns of a second conductivity-type, a plane pattern of each of the columns extends along a parallel direction to the principal surface of the layer, the columns are arranged at regular intervals; a plurality of well regions of the second conductivity-type provided in a surface-side layer of the layer of the first conductivity-type; a plurality of source regions of the first conductivity-type selectively provided in the plurality of well regions; a gate insulating film provided on the principal surface; an array of gate electrodes disposed on the gate insulating film, each of the gate electrodes is provided so as to bridge the corresponding source regions in a pair of neighboring two well regions; and a temperature detection diode provided at a partial area defined in the array of the gate electrodes.

Abstract: An n-type region and a p-type region of a first parallel pn layer are arranged parallel to a base front surface, in a striped planar layout extending from an active region over an edge termination region. In the n-type region, a gate trench extending linearly along a first direction is provided. In an intermediate region, in a surface region on the base front surface side of the first parallel pn layer, a second parallel pn layer is provided. The second parallel pn layer is arranged having a repetition cycle shifted along a second direction ½ a cell with respect to a repetition cycle of the n-type region and the p-type region of the first parallel pn layer. A gate trench termination portion terminates in the intermediate region between the active region and the edge termination region, and is covered by the p-type region of the second parallel pn layer.

Abstract: To suppress the reverse breakdown voltage decrease while separating a main body region from a current detecting region. To provide a semiconductor device comprising a semiconductor substrate, a main body region having one or more operation cells formed inside the semiconductor substrate, a current detecting region having one or more current detecting cells formed inside the semiconductor substrate, an intermediate region formed between the main body region and the current detecting region and inside the semiconductor substrate, an upper surface side electrode formed above at least part of the main body region, a current detecting electrode that is formed above at least part of the current detecting region and is separate from the upper surface side electrode, and an additional electrode that is formed above at least part of the intermediate region and is connected to either the upper surface side electrode or the current detecting electrode.

Abstract: In a conventional semiconductor chip, the source electrode and the sense pad electrode for current detection are provided separately and distanced from each other on the front surface of the semiconductor chip. The area occupied by the sense pad electrode must be several times the area of a MOSFET cell unit. Therefore, there is a problem that the area of the sense pad electrode is enlarged relative to the source electrode. Provided is a semiconductor device including a semiconductor substrate; a front surface electrode provided above the semiconductor substrate; a first wire for a first terminal connected to the front surface electrode; and a second wire for current sensing connected to the front surface electrode. A resistance of a path through which current flows through the second wire is higher than a resistance of a path through which the current flows through the first wire.

Abstract: In a semiconductor device having an SJ structure, the reverse breakdown voltage decrease is suppressed while a main body region and a current detecting region are separated. Provided is a semiconductor device that has a semiconductor substrate, a main body region including one or more operation cells formed inside the semiconductor substrate, a current detecting region including one or more current detecting cells formed inside the semiconductor substrate, and an intermediate region that is provided between the main body region and the current detecting region and inside the semiconductor substrate and that includes an edge termination structure unit. A first conductivity-type column and a second conductivity-type column are alternately arranged at equal intervals in the main body region, the current detecting region, and the intermediate region.

Abstract: To suppress the reverse breakdown voltage decrease while separating a main body region from a current detecting region. To provide a semiconductor device comprising a semiconductor substrate, a main body region having one or more operation cells formed inside the semiconductor substrate, a current detecting region having one or more current detecting cells formed inside the semiconductor substrate, an intermediate region formed between the main body region and the current detecting region and inside the semiconductor substrate, an upper surface side electrode formed above at least part of the main body region, a current detecting electrode that is formed above at least part of the current detecting region and is separate from the upper surface side electrode, and an additional electrode that is formed above at least part of the intermediate region and is connected to either the upper surface side electrode or the current detecting electrode.

Abstract: To provide a semiconductor device having a structure capable of forming a superjunction with less thermal history, a semiconductor device is provided, the semiconductor device including a contact trench formed between two gate trenches, penetrating through a source region, and including its lower end arranged in a base region, and a second conductivity-type protruding portion formed protruding toward a lower side from the lower end of the base region in a region opposite to the lower end of the contact trench, wherein the depth from the upper end of the source region to a lower end of the protruding portion is 3 ?m or more, and a carrier concentration Nd in a first conductivity-type region adjacent to the protruding portion in a lateral direction perpendicular to a depth direction and a carrier concentration Na of the protruding portion satisfy a predetermined equation.

Abstract: A mask used to form an n+ source layer (11) is formed by a nitride film on the surface of a substrate before a trench (7) is formed. At this time, a sufficient width of the n+ source layer (11) on the surface of the substrate is secured. Thereby, stable contact between the n+ source layer (11) and a source electrode (15) is obtained. A CVD oxide film (12) that is an interlayer insulating film having a thickness of 0.1 micrometer or more and 0.3 micrometer or less is formed on doped poly-silicon to be used as a gate electrode (10a) embedded in the trench (7), and non-doped poly-silicon (13) that is not oxidized is formed on the CVD oxide film (12). Thereby, generation of void in the CVD oxide film (12) is suppressed and, by not oxidizing the non-doped poly-silicon (13), a semiconductor apparatus is easily manufactured.

Abstract: In a conventional semiconductor chip, the source electrode and the sense pad electrode for current detection are provided separately and distanced from each other on the front surface of the semiconductor chip. The area occupied by the sense pad electrode must be several times the area of a MOSFET cell unit. Therefore, there is a problem that the area of the sense pad electrode is enlarged relative to the source electrode. Provided is a semiconductor device including a semiconductor substrate; a front surface electrode provided above the semiconductor substrate; a first wire for a first terminal connected to the front surface electrode; and a second wire for current sensing connected to the front surface electrode. A resistance of a path through which current flows through the second wire is higher than a resistance of a path through which the current flows through the first wire.

Abstract: A semiconductor device in which current sensing accuracy is maintained while ruggedness of a current sensing region is improved. The semiconductor device includes a semiconductor substrate; a main element provided on the semiconductor substrate and having a first trench gate structure including a first trench disposed on a first main surface side of the semiconductor substrate; a gate insulating film disposed along an inner wall of the first trench; and a gate electrode disposed inside the first trench; and a current detecting element for detecting a current flowing into the semiconductor substrate when the main element is operating provided on the semiconductor substrate and having a second trench gate structure including a second trench disposed on the first main surface side of the semiconductor substrate; the gate insulating film disposed along an inner wall of the second trench; and the gate electrode disposed inside the second trench.

Abstract: A deterioration of a gate threshold voltage, which is caused by a stress and a thermal hysteresis when wire bonding for a surface of an electrode layer of a semiconductor device is performed, can be suppressed. The semiconductor device includes a metallic film provided at a surface of a semiconductor chip, and a wire bonded to an upper surface of the metallic film. The metallic film has a plurality of grains, particle diameters of the grains are substantially equal to or more than a thickness of the metallic film.

Abstract: Provided is a semiconductor device manufacturing method such that miniaturization of a parallel p-n layer can be achieved, and on-state resistance can be reduced. Firstly, deposition of an n?-type epitaxial layer, and formation of an n-type impurity region and p-type impurity region that form an n-type region and p-type region of a parallel p-n layer, are repeatedly carried out. Furthermore, an n?-type counter region is formed in the vicinity of the p-type impurity region in the uppermost n?-type epitaxial layer forming the parallel p-n layer. Next, an n?-type epitaxial layer is deposited on the n?-type epitaxial layer. Next, a MOS gate structure is formed in the n?-type epitaxial layer. At this time, when carrying out a p-type base region diffusion process, the n-type and p-type impurity regions are caused to diffuse, thereby forming the n-type region and p-type region of the parallel p-n layer.

Abstract: A mask used to form an n+ source layer (11) is formed by a nitride film on the surface of a substrate before a trench (7) is formed. At this time, a sufficient width of the n+ source layer (11) on the surface of the substrate is secured. Thereby, stable contact between the n+ source layer (11) and a source electrode (15) is obtained. A CVD oxide film (12) that is an interlayer insulating film having a thickness of 0.1 micrometer or more and 0.3 micrometer or less is formed on doped poly-silicon to be used as a gate electrode (10a) embedded in the trench (7), and non-doped poly-silicon (13) that is not oxidized is formed on the CVD oxide film (12). Thereby, generation of void in the CVD oxide film (12) is suppressed and, by not oxidizing the non-doped poly-silicon (13), a semiconductor apparatus is easily manufactured.

Abstract: A MOS semiconductor device has a MOS structure, including a p? region that surrounds an n+-type source region and has a net doping concentration lower than a concentration of a p-type impurity in a surface of a p-type well region, and a gate electrode that is provided on top of the surface of the p-type well region sandwiched between the n+-type source region and a surface layer of an n? layer, with a gate insulator disposed between the p-type well region and the gate electrode. This configuration can make the gate insulator thicker without increasing a gate threshold voltage, and help improve the reliability of the gate insulator and reduce the gate capacitance.

Abstract: A method for manufacturing a semiconductor device is disclosed in which the probability of occurrence of a crack is reduced and in which manufacturing cost is also reduced. An exposure mask used in the method is disclosed. Protrusion portions are formed in intersections of scribe lines in an outermost periphery of a scribe line pattern of a surface protection film of the exposure mask, to thereby stick out toward an outer circumference. In this manner, the probability of occurrence of a crack occurring in a device formation section can be reduced so that a reduction in the manufacturing cost can be achieved.

Abstract: A semiconductor device according to the invention includes p-type well region 3 and n+ source region 4, both formed selectively in the surface portion of n? drift region 2; trench 6 in contact with n+ source region 4 and extending through p-type well region 3 into n? drift region 2; field plate 8 formed in trench 6 with first insulator film 7 interposed between the trench 6 inner surface and field plate 8; gate electrode 10 formed in trench 6 with second insulator film 9 interposed between the trench 6 side wall and gate electrode 10, gate electrode 10 being formed above field plate 8; first insulator film 7 being thicker than second insulator film 9; and n? lightly doped region 21 in n? drift region 2, n? lightly doped region 21 crossing under the bottom surface of trench 6 from the corner portion thereof, n? lightly doped region 21 covering the bottom surface of trench 6.

Abstract: A semiconductor device includes a drift layer of a first conductivity-type, having a superjunction structure, including a plurality of columns of a second conductivity-type, a plane pattern of each of the columns extends along a parallel direction to the principal surface of the layer, the columns are arranged at regular intervals; a plurality of well regions of the second conductivity-type provided in a surface-side layer of the layer of the first conductivity-type; a plurality of source regions of the first conductivity-type selectively provided in the plurality of well regions; a gate insulating film provided on the principal surface; an array of gate electrodes disposed on the gate insulating film, each of the gate electrodes is provided so as to bridge the corresponding source regions in a pair of neighboring two well regions; and a temperature detection diode provided at a partial area defined in the array of the gate electrodes.

Abstract: A mask used to form an n+ source layer (11) is formed by a nitride film on the surface of a substrate before a trench (7) is formed. At this time, a sufficient width of the n+ source layer (11) on the surface of the substrate is secured. Thereby, stable contact between the n+ source layer (11) and a source electrode (15) is obtained. A CVD oxide film (12) that is an interlayer insulating film having a thickness of 0.1 micrometer or more and 0.3 micrometer or less is formed on doped poly-silicon to be used as a gate electrode (10a) embedded in the trench (7), and non-doped poly-silicon (13) that is not oxidized is formed on the CVD oxide film (12). Thereby, generation of void in the CVD oxide film (12) is suppressed and, by not oxidizing the non-doped poly-silicon (13), a semiconductor apparatus is easily manufactured.