Abstract: An image processing unit includes a candidate pixel group determiner to specify each pixel of an image to be processed as pixel of interest, extract pixels having divergence in position in a certain range from the pixel of interest, and determine, from the extracted pixels, pixels having divergence in pixel value in a certain range from the pixel of interest as a candidate pixel group, an associator to associate the candidate pixel group with the pixel of interest, and an image processor to perform image processing on the candidate pixel group associated with the pixel of interest. The image processor selects, from the candidate pixel group, pixels having divergence in pixel value in a certain range from the pixel of interest as a pixel group to be processed, and smoothes the pixel value of the pixel of interest in accordance with each pixel value of the candidate pixel group.

Abstract: A screen oxide film is formed on an n? drift layer (2) that is disposed on an anterior side of an n-type low-resistance layer (1), and a nitride film is formed on the screen oxide film. The nitride film is photo-etched using a first mask and thereby, a nitride shielding film (61) is formed. N-type impurity ions at a concentration higher than that of the n-drift layer are implanted through the nitride shielding film (61) from an anterior side of a semiconductor substrate and are thermally diffused and thereby, an n counter layer (7) is formed. The screen oxide film is removed. A gate oxide film (3a) is formed. A gate electrode (9) is formed on the gate oxide film (3a). P-type impurity ions are implanted from the anterior side of the semiconductor substrate using the gate electrode (9) and the nitride shielding film (61) as a mask and thereby, p? well regions (10) are formed.

Abstract: A semiconductor device according to the invention includes p-type well region 3 and n+ source region 4, both formed selectively in the surface portion of n? drift region 2; trench 6 in contact with n+ source region 4 and extending through p-type well region 3 into n? drift region 2; field plate 8 formed in trench 6 with first insulator film 7 interposed between the trench 6 inner surface and field plate 8; gate electrode 10 formed in trench 6 with second insulator film 9 interposed between the trench 6 side wall and gate electrode 10, gate electrode 10 being formed above field plate 8; first insulator film 7 being thicker than second insulator film 9; and n?? lightly doped region 21 in n? drift region 2, n?? lightly doped region 21 crossing under the bottom surface of trench 6 from the corner portion thereof, n?? lightly doped region 21 covering the bottom surface of trench 6.

Abstract: A method of manufacturing a MOS-type semiconductor device capable of increasing the thickness of a gate oxide film and obtaining high gate withstanding power and reduced switching loss without increasing a gate threshold voltage Vth is provided. A p-type well region is selectively formed on one principle surface of a semiconductor substrate having an n-type low impurity concentration layer by using an oxide film as a mask. Subsequently, a resist mask is formed on the surface of the p-type well region so as to be separated from the oxide film mask, and an n+-type source region is selectively formed from the separation portion. Subsequently, the oxide film mask is removed. Then, an oxide film is formed on the surface of the p-type well region, and the oxide film is removed. Subsequently, a gate electrode coated with a gate oxide film is formed on the surface of the semiconductor substrate.

Abstract: A semiconductor device includes a p-type well region 3 and an n+ source region 4, both formed selectively in the surface portion of n? drift region 2. A trench 6 is in contact with n+ source region 4 and extends through p-type well region 3 into n? drift region 2. A field plate 8 is formed in trench 6, with a first insulator film 7 being interposed between the trench 6 surface and field plate 8. A gate electrode 10 is formed in trench 6 above field plate 10, with a second insulator film 9 being interposed between the trench 6 surface and gate electrode 10. An n?? lightly doped region 21 in n? drift region 2 crosses under the bottom of trench 6.

Abstract: A capacitive component region is formed below a temperature detecting diode or below a protective diode. In addition, the capacitive component region is formed below an anode metal wiring line connecting the temperature detecting diode and an anode electrode pad and below a cathode metal wiring line connecting the temperature detecting diode and a cathode electrode pad. The capacitive component region is an insulating film interposed between polysilicon layers. Specifically, a first insulating film, a polysilicon conductive layer, and a second insulating film are sequentially formed on a first main surface of a semiconductor substrate, and the temperature detecting diode, the protective diode, the anode metal wiring line, or the cathode metal wiring line is formed on the upper surface of the second insulating film. Therefore, it is possible to improve the static electricity resistance of the temperature detecting diode or the protective diode.

Abstract: A method for manufacturing a semiconductor device is disclosed in which the probability of occurrence of a crack is reduced and in which manufacturing cost is also reduced. An exposure mask used in the method is disclosed. Protrusion portions are formed in intersections of scribe lines in an outermost periphery of a scribe line pattern of a surface protection film of the exposure mask, to thereby stick out toward an outer circumference. In this manner, the probability of occurrence of a crack occurring in a device formation section can be reduced so that a reduction in the manufacturing cost can be achieved.

Abstract: An image processing unit includes a candidate pixel group determiner to specify each pixel of an image to be processed as pixel of interest, extract pixels having divergence in position in a certain range from the pixel of interest, and determine, from the extracted pixels, pixels having divergence in pixel value in a certain range from the pixel of interest as a candidate pixel group, an associator to associate the candidate pixel group with the pixel of interest, and an image processor to perform image processing on the candidate pixel group associated with the pixel of interest. The image processor selects, from the candidate pixel group, pixels having divergence in pixel value in a certain range from the pixel of interest as a pixel group to be processed, and smoothes the pixel value of the pixel of interest in accordance with each pixel value of the candidate pixel group.

Abstract: A MOS semiconductor device has a MOS structure, including a p? region that surrounds an n+-type source region and has a net doping concentration lower than a concentration of a p-type impurity in a surface of a p-type well region, and a gate electrode that is provided on top of the surface of the p-type well region sandwiched between the n+-type source region and a surface layer of an n? layer, with a gate insulator disposed between the p-type well region and the gate electrode. This configuration can make the gate insulator thicker without increasing a gate threshold voltage, and help improve the reliability of the gate insulator and reduce the gate capacitance.

Abstract: A semiconductor device includes a p-type well region 3 and an n+ source region 4, both formed selectively in the surface portion of n? drift region 2. A trench 6 is in contact with n+ source region 4 and extends through p-type well region 3 into n? drift region 2. A field plate 8 is formed in trench 6, with a first insulator film 7 being interposed between the trench 6 surface and field plate 8. A gate electrode 10 is formed in trench 6 above field plate 10, with a second insulator film 9 being interposed between the trench 6 surface and gate electrode 10. An n?? lightly doped region 21 in n? drift region 2 crosses under the bottom of trench 6.

Abstract: A semiconductor device according to the invention includes p-type well region 3 and n+ source region 4, both formed selectively in the surface portion of n? drift region 2; trench 6 in contact with n+ source region 4 and extending through p-type well region 3 into n? drift region 2; field plate 8 formed in trench 6 with first insulator film 7 interposed between the trench 6 inner surface and field plate 8; gate electrode 10 formed in trench 6 with second insulator film 9 interposed between the trench 6 side wall and gate electrode 10, gate electrode 10 being formed above field plate 8; first insulator film 7 being thicker than second insulator film 9; and n?? lightly doped region 21 in n? drift region 2, n?? lightly doped region 21 crossing under the bottom surface of trench 6 from the corner portion thereof, n?? lightly doped region 21 covering the bottom surface of trench 6.

Abstract: A mask used to form an n+ source layer (11) is formed by a nitride film on the surface of a substrate before a trench (7) is formed. At this time, a sufficient width of the n+ source layer (11) on the surface of the substrate is secured. Thereby, stable contact between the n+ source layer (11) and a source electrode (15) is obtained. A CVD oxide film (12) that is an interlayer insulating film having a thickness of 0.1 micrometer or more and 0.3 micrometer or less is formed on doped poly-silicon to be used as a gate electrode (10a) embedded in the trench (7), and non-doped poly-silicon (13) that is not oxidized is formed on the CVD oxide film (12). Thereby, generation of void in the CVD oxide film (12) is suppressed and, by not oxidizing the non-doped poly-silicon (13), a semiconductor apparatus is easily manufactured.

Abstract: A screen oxide film is formed on an n? drift layer (2) that is disposed on an anterior side of an n-type low-resistance layer (1), and a nitride film is formed on the screen oxide film. The nitride film is photo-etched using a first mask and thereby, a nitride shielding film (61) is formed. N-type impurity ions at a concentration higher than that of the n? drift layer are implanted through the nitride shielding film (61) from an anterior side of a semiconductor substrate and are thermally diffused and thereby, an n counter layer (7) is formed. The screen oxide film is removed. A gate oxide film (3a) is formed. A gate electrode (9) is formed on the gate oxide film (3a). P-type impurity ions are implanted from the anterior side of the semiconductor substrate using the gate electrode (9) and the nitride shielding film (61) as a mask and thereby, p? well regions (10) are formed.

Abstract: A semiconductor device according to the invention includes p-type well region 3 and n+ source region 4, both formed selectively in the surface portion of n? drift region 2; trench 6 in contact with n+ source region 4 and extending through p-type well region 3 into n? drift region 2; field plate 8 formed in trench 6 with first insulator film 7 interposed between the trench 6 inner surface and field plate 8; gate electrode 10 formed in trench 6 with second insulator film 9 interposed between the trench 6 side wall and gate electrode 10, gate electrode 10 being formed above field plate 8; first insulator film 7 being thicker than second insulator film 9; and n?? lightly doped region 21 in n? drift region 2, n?? lightly doped region 21 crossing under the bottom surface of trench 6 from the corner portion thereof, n?? lightly doped region 21 covering the bottom surface of trench 6.

Abstract: A p? RESURF region is formed as a surface layer in an n? semiconductor layer. Then, trenches, gate insulating films, and a thick insulating film, gate electrodes, and a gate polysilicon interconnection are formed in this order. Subsequently, a p-well region is formed using the gate polysilicon interconnection as a mask. Then n+ source regions are formed. Since the p? RESURF region is formed and the p-well region is formed after forming the gate electrodes and the gate polysilicon interconnection, the severeness of a high-temperature heat history is lowered and the diffusion depth of the p-well region is decreased. The formation of the p? RESURF region and the shallow p-well region makes it possible to reduce the on-resistance while increasing the breakdown voltage, as well as reducing the gate capacitance.

Abstract: A semiconductor device is provided with Zener diodes which are formed by using a polysilicon gate layer(s) so as to be connected to each other in parallel. Parallel-connected rectangular Zener diodes are formed outside an active region or parallel-connected striped Zener diodes are formed inside the active region. The Zener diodes increase the ESD capability of the semiconductor device.

Abstract: A p? RESURF region is formed as a surface layer in an n? semiconductor layer. Then, trenches, gate insulating films, and a thick insulating film, gate electrodes, and a gate polysilicon interconnection are formed in this order. Subsequently, a p-well region is formed using the gate polysilicon interconnection as a mask. Then n+ source regions are formed. Since the p? RESURF region is formed and the p-well region is formed after forming the gate electrodes and the gate polysilicon interconnection, the severeness of a high-temperature heat history is lowered and the diffusion depth of the p-well region is decreased. The formation of the p? RESURF region and the shallow p-well region makes it possible to reduce the on-resistance while increasing the breakdown voltage, as well as reducing the gate capacitance.

Abstract: A semiconductor device is provided with Zener diodes which are formed by using a polysilicon gate layer(s) so as to be connected to each other in parallel. Parallel-connected rectangular Zener diodes are formed outside an active region or parallel-connected striped Zener diodes are formed inside the active region. The Zener diodes increase the ESD capability of the semiconductor device.

Abstract: The superjunction semiconductor device includes a drain drift section, which includes a first alternating conductivity type layer formed of first n-type regions and first p-type regions arranged alternately. The device also includes a peripheral section around the drain drift section, which includes a second alternating conductivity type layer formed of second n-type regions and second p-type regions arranged alternately. The peripheral section further includes a third alternating conductivity type layer in its surface portion. The third alternating conductivity type layer is formed of third n-type regions and third p-type regions arranged alternately. At least the peripheral section is configured to improve the avalanche withstanding capability over the entire device.

Abstract: A semiconductor device includes an active region, an alternating conductivity type layer, and an insulation region surrounding the alternating conductivity type layer provided in a periphery section as a voltage withstanding section. The insulation region is made of an insulator with the critical electric field strength higher than that of the semiconductor and reaches an n+-drain layer on the bottom surface side of the device from a surface on the side on which a surface structure section is formed. In the alternating conductivity type layer, the width of the p-type partition region adjacent to the insulation region is made narrower than the width of the p-type partition region not adjacent to the insulation region to ensure a balanced state of charges at the end of the drift section made up of the alternating conductivity type layer. A high breakdown voltage is ensured with the length of the periphery section shortened.