Patents by Inventor Taku Horii

Taku Horii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210265469
    Abstract: A silicon carbide semiconductor device to be a vertical transistor includes: a silicon carbide semiconductor first layer 21 of a first conductivity type; a silicon carbide semiconductor second layer 22 of a second conductivity type that is different from the first conductivity type on the first layer 21; a silicon carbide semiconductor third layer 120 of the first conductivity type on the second layer 22; and a groove 30 having a sidewall 30a at portions of the third layer 120, the second layer 22, and the first layer 21, wherein the third layer 120 has a first area 121 facing the sidewall 30a of the groove 30 and a second area 122 further away from the sidewall 30a of the groove 30 than the first area 121, wherein the second area 122 and the first area 121 are continuous, and wherein the second area 122 is provided deeper than the first area 121 from a surface side of the third layer 130 toward the first layer 21.
    Type: Application
    Filed: June 13, 2019
    Publication date: August 26, 2021
    Inventors: Taku HORII, Toru HIYOSHI
  • Patent number: 10468358
    Abstract: A method of manufacturing a semiconductor device includes the steps of preparing a semiconductor layer including a wide bandgap semiconductor, the semiconductor layer having an element region and an outer peripheral region surrounding an outer periphery of the element region when viewed two-dimensionally, forming a step portion surrounding the outer periphery of the element region in the outer peripheral region, and forming a metal layer along the step portion. The step portion has a sidewall recessed downward from a main surface of the element region in a cross section parallel to a thickness direction of the semiconductor layer, and the metal layer extends to cover at least a portion of the sidewall. The method of manufacturing a semiconductor device further includes the step of dividing the semiconductor layer into the element regions on an outside of the step portion when viewed from the element region.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: November 5, 2019
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Toru Hiyoshi, Taku Horii
  • Patent number: 10340344
    Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate, a gate insulating film, and a gate electrode. The gate insulating film is provided as being in contact with the first main surface of the silicon carbide substrate. The gate electrode is provided on the gate insulating film such that the gate insulating film lies between the gate electrode and the silicon carbide substrate. In a first stress test in which a gate voltage of ?5 V is applied to the gate electrode for 100 hours at a temperature of 175° C., an absolute value of a difference between a first threshold voltage and a second threshold voltage is not more than 0.5 V, with a threshold voltage before the first stress test being defined as the first threshold voltage and a threshold voltage after the first stress test being defined as the second threshold voltage.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: July 2, 2019
    Assignees: Sumitomo Electric Industries, Ltd., Renesas Electronics Corporation
    Inventors: Ryosuke Kubota, Shunsuke Yamada, Taku Horii, Takeyoshi Masuda, Daisuke Hamajima, So Tanaka, Shinji Kimura, Masayuki Kobayashi
  • Patent number: 10050109
    Abstract: A silicon carbide semiconductor substrate includes: a base substrate that has a main surface having an outer diameter of not less than 100 mm and that is made of single-crystal silicon carbide; and an epitaxial layer formed on the main surface. The silicon carbide semiconductor substrate has an amount of warpage of not less than ?100 ?m and not more than 100 ?m when a substrate temperature is a room temperature and has an amount of warpage of not less than ?1.5 mm and not more than 1.5 mm when the substrate temperature is 400° C.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: August 14, 2018
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Taku Horii, Ryosuke Kubota, Takeyoshi Masuda
  • Publication number: 20180138275
    Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate, a gate insulating film, and a gate electrode. The gate insulating film is provided as being in contact with the first main surface of the silicon carbide substrate. The gate electrode is provided on the gate insulating film such that the gate insulating film lies between the gate electrode and the silicon carbide substrate. In a first stress test in which a gate voltage of ?5 V is applied to the gate electrode for 100 hours at a temperature of 175° C., an absolute value of a difference between a first threshold voltage and a second threshold voltage is not more than 0.5 V, with a threshold voltage before the first stress test being defined as the first threshold voltage and a threshold voltage after the first stress test being defined as the second threshold voltage.
    Type: Application
    Filed: January 12, 2018
    Publication date: May 17, 2018
    Inventors: Ryosuke Kubota, Shunsuke Yamada, Taku Horii, Takeyoshi Masuda, Daisuke Hamajima, So Tanaka, Shinji Kimura, Masayuki Kobayashi
  • Patent number: 9966437
    Abstract: Included are the steps of: preparing a silicon carbide substrate having an epitaxial layer formed thereon; forming an upper-layer film on the epitaxial layer; and removing at least a portion of the upper-layer film in an outer peripheral portion of the silicon carbide substrate, and patterning the upper-layer film.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: May 8, 2018
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Taku Horii
  • Patent number: 9905653
    Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate, a gate insulating film, and a gate electrode. The gate insulating film is provided as being in contact with the first main surface of the silicon carbide substrate. The gate electrode is provided on the gate insulating film such that the gate insulating film lies between the gate electrode and the silicon carbide substrate. In a first stress test in which a gate voltage of ?5 V is applied to the gate electrode for 100 hours at a temperature of 175° C., an absolute value of a difference between a first threshold voltage and a second threshold voltage is not more than 0.5 V, with a threshold voltage before the first stress test being defined as the first threshold voltage and a threshold voltage after the first stress test being defined as the second threshold voltage.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: February 27, 2018
    Assignees: Sumitomo Electric Industries, Ltd., Renesas Electronics Corporation
    Inventors: Ryosuke Kubota, Shunsuke Yamada, Taku Horii, Takeyoshi Masuda, Daisuke Hamajima, So Tanaka, Shinji Kimura, Masayuki Kobayashi
  • Publication number: 20180019215
    Abstract: A method of manufacturing a semiconductor device includes the steps of preparing a semiconductor layer including a wide bandgap semiconductor, the semiconductor layer having an element region and an outer peripheral region surrounding an outer periphery of the element region when viewed two-dimensionally, forming a step portion surrounding the outer periphery of the element region in the outer peripheral region, and forming a metal layer along the step portion. The step portion has a sidewall recessed downward from a main surface of the element region in a cross section parallel to a thickness direction of the semiconductor layer, and the metal layer extends to cover at least a portion of the sidewall. The method of manufacturing a semiconductor device further includes the step of dividing the semiconductor layer into the element regions on an outside of the step portion when viewed from the element region.
    Type: Application
    Filed: August 15, 2017
    Publication date: January 18, 2018
    Inventors: Toru Hiyoshi, Taku Horii
  • Patent number: 9818608
    Abstract: A silicon carbide semiconductor substrate includes: a base substrate that has a main surface having an outer diameter of not less than 100 mm and that is made of single-crystal silicon carbide; an epitaxial layer formed on the main surface; and a deformation suppression layer formed on a backside surface of the base substrate opposite to the main surface. In this way, the deformation suppression layer suppresses the substrate from being deformed (for example, warped during high-temperature treatment). This can reduce a risk of causing defects such as crack in the silicon carbide semiconductor substrate during the manufacturing process in performing a method for manufacturing a silicon carbide semiconductor device using the silicon carbide semiconductor substrate.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: November 14, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Taku Horii, Takeyoshi Masuda
  • Patent number: 9806167
    Abstract: The steps of preparing a silicon carbide layer having a main surface, forming on the main surface, a first mask layer located on a first region to be a channel region and having a first opening portion on each of opposing regions with the first region lying therebetween, and forming a high-concentration impurity region having a first conductivity type and being higher in impurity concentration than the silicon carbide layer in a region exposed through the first opening portion, by implanting ions into the main surface with the first mask layer being interposed are included.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: October 31, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Taku Horii, Takeyoshi Masuda, Ryosuke Kubota
  • Patent number: 9786741
    Abstract: A silicon carbide semiconductor device includes a silicon carbide layer and a gate insulating layer. The silicon carbide layer has a main surface. The gate insulating layer is arranged as being in contact with the main surface of the silicon carbide layer. The silicon carbide layer includes a drift region having a first conductivity type, a body region having a second conductivity type different from the first conductivity type and being in contact with the drift region, a source region having the first conductivity type and arranged as being spaced apart from the drift region by the body region, and a protruding region arranged to protrude from at least one side of the source region and the drift region into the body region, being in contact with the gate insulating layer, and having the first conductivity type.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: October 10, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takeyoshi Masuda, Taku Horii, Ryosuke Kubota
  • Patent number: 9768125
    Abstract: A method of manufacturing a semiconductor device includes preparing a semiconductor layer having an element region and an outer peripheral region, forming a step portion surrounding the outer periphery of the element region in the outer peripheral region, and forming a metal layer along the step portion. The metal layer extends to cover at least a portion of a sidewall of the step portion. The method of manufacturing the semiconductor device further includes dividing the semiconductor layer into element regions on an outside of the step portion when viewed from the element region.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: September 19, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Toru Hiyoshi, Taku Horii
  • Patent number: 9741799
    Abstract: A silicon carbide semiconductor device includes a silicon carbide semiconductor layer, a gate insulating film formed on the silicon carbide semiconductor layer, and a gate electrode provided on the gate insulating film, wherein the gate electrode has a polysilicon layer at least on a side of an interface with the gate insulating film, and the gate insulating film has an oxide film derived from the polysilicon layer, at an interface between the gate insulating film and the polysilicon layer of the gate electrode.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: August 22, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Toru Hiyoshi, Taku Horii, Takeyoshi Masuda, Shunsuke Yamada
  • Patent number: 9728607
    Abstract: A silicon carbide substrate having a gate insulating film provided in contact with a first main surface, having a gate electrode provided in contact with the gate insulating film, and having a source region exposed from first main surface is prepared. A first recess having a first inner wall surface is formed in an interlayer insulating film by performing a first isotropic etching with respect to the interlayer insulating film with use of a mask layer. A second recess having a second inner wall surface is formed by performing a first anisotropic etching with respect to the interlayer insulating film and the gate insulating film with use of the mask layer and thereby exposing the source region from gate insulating film. An interconnection is formed which is arranged in contact with the first inner wall surface and the second inner wall surface and electrically connected to a source electrode.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: August 8, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Taku Horii, Masaki Kijima
  • Patent number: 9728628
    Abstract: A silicon carbide epitaxial layer includes: a first impurity region; a second impurity region; and a third impurity region. A gate insulating film is in contact with the first impurity region, the second impurity region, and the third impurity region. A groove portion is formed in a surface of the first impurity region, the surface being in contact with the gate insulating film, the groove portion extending in one direction along the surface, a width of the groove portion in the one direction being twice or more as large as a width of the groove portion in a direction perpendicular to the one direction, a maximum depth of the groove portion from the surface being not more than 10 nm.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: August 8, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Wada, Taro Nishiguchi, Toru Hiyoshi, Taku Horii, Kosuke Uchida
  • Patent number: 9691616
    Abstract: A method of manufacturing a silicon carbide semiconductor device includes a step of preparing a silicon carbide substrate having a first main surface and a second main surface located opposite to the first main surface, a step of forming a doped region in the silicon carbide substrate by doping the first main surface with an impurity, a step of forming a first protecting film on the first main surface, and a step of forming a second protecting film on the second main surface, the step of forming a first protecting film being performed after the step of forming a doped region, the method further including a step of activating the impurity included in the doped region by annealing with at least a portion of the first main surface covered with the first protecting film and at least a portion of the second main surface covered with the second protecting film.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: June 27, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Taku Horii
  • Patent number: 9691608
    Abstract: A method for manufacturing a silicon carbide substrate includes the following steps. There is prepared a silicon carbide single crystal substrate having a first main surface, a second main surface, and a first side end portion, the second main surface being opposite to the first main surface, the first side end portion connecting the first main surface and the second main surface to each other, the first main surface having a width with a maximum value of more than 100 mm. A silicon carbide epitaxial layer is formed in contact with the first side end portion, the first main surface, and a boundary between the first main surface and the first side end portion. The silicon carbide epitaxial layer formed in contact with the first side end portion and the boundary is removed.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: June 27, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: So Tanaka, Shunsuke Yamada, Taku Horii, Akira Matsushima, Ryosuke Kubota, Kyoko Okita, Takayuki Nishiura
  • Patent number: 9653297
    Abstract: A method of manufacturing a silicon carbide semiconductor device includes a step of preparing a silicon carbide substrate having a first main surface and a second main surface located opposite to the first main surface, a step of forming a doped region in the silicon carbide substrate by doping the first main surface with an impurity, a step of forming a first protecting film on the doped region at the first main surface, and a step of activating the impurity included in the doped region by annealing with the first protecting film having been formed, the step of forming a first protecting film including a step of disposing a material which will form the first protecting film and in which the concentration of a metal element is less than or equal to 5 ?g/kg on the first main surface.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: May 16, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Taku Horii, Tomoaki Ishida
  • Patent number: 9613809
    Abstract: A method of manufacturing a silicon carbide semiconductor device includes the following steps. A silicon carbide substrate is prepared. A first mask layer is formed in contact with a first main surface of the silicon carbide substrate. The first mask layer includes a first layer disposed in contact with the first main surface, an etching stop layer disposed in contact with the first layer and made of a material different from that for the first layer, and a second layer disposed in contact with a surface of the etching stop layer opposite to the surface in contact with the first layer. A recess is formed in the first mask layer by etching the second layer and the etching stop layer. A first impurity region is formed in the silicon carbide substrate using the first mask layer with the recess. The first mask layer does not include a metallic element.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: April 4, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Taku Horii, Masaki Kijima
  • Patent number: 9583346
    Abstract: A method for manufacturing a silicon carbide semiconductor device includes steps below. A silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, the first main surface having a maximal diameter greater than 100 mm, is prepared. An impurity region is formed on a side of the first main surface of the silicon carbide substrate. In a plan view, a cover member is arranged on the side of the first main surface so as to cover at least the entire impurity region. The silicon carbide substrate is annealed at a temperature lower than a melting point of the cover member while the cover member is arranged on the side of the first main surface of the silicon carbide substrate.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: February 28, 2017
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Shunsuke Yamada, Takeyoshi Masuda, Taku Horii