Patents by Inventor Taku Horii

Taku Horii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150380247
    Abstract: A method of manufacturing a silicon carbide semiconductor device includes the following steps. A silicon carbide substrate is prepared. A first mask layer is formed in contact with a first main surface of the silicon carbide substrate. The first mask layer includes a first layer disposed in contact with the first main surface, an etching stop layer disposed in contact with the first layer and made of a material different from that for the first layer, and a second layer disposed in contact with a surface of the etching stop layer opposite to the surface in contact with the first layer. A recess is formed in the first mask layer by etching the second layer and the etching stop layer. A first impurity region is formed in the silicon carbide substrate using the first mask layer with the recess. The first mask layer does not include a metallic element.
    Type: Application
    Filed: January 17, 2014
    Publication date: December 31, 2015
    Inventors: Taku HORII, Masaki KIJIMA
  • Publication number: 20150372094
    Abstract: A silicon carbide substrate having a gate insulating film provided in contact with a first main surface, having a gate electrode provided in contact with the gate insulating film, and having a source region exposed from first main surface is prepared. A first recess having a first inner wall surface is formed in an interlayer insulating film by performing a first isotropic etching with respect to the interlayer insulating film with use of a mask layer. A second recess having a second inner wall surface is formed by performing a first anisotropic etching with respect to the interlayer insulating film and the gate insulating film with use of the mask layer and thereby exposing the source region from gate insulating film. An interconnection is formed which is arranged in contact with the first inner wall surface and the second inner wall surface and electrically connected to a source electrode.
    Type: Application
    Filed: January 17, 2014
    Publication date: December 24, 2015
    Inventors: Taku HORII, Masaki KIJIMA
  • Patent number: 9177856
    Abstract: A MOSFET includes: a substrate; a gate insulating film; a gate electrode; an interlayer insulating film formed on the gate insulating film to surround the gate electrode; a buffer film containing Ti and N and containing no Al; and a source electrode containing Ti, Al, and Si. In the MOSFET, a contact hole is formed away from the gate electrode so as to extend through the interlayer insulating film and expose a main surface of the substrate. The buffer film is formed in contact with a side wall surface of the contact hole. The source electrode is formed on and in contact with the buffer film and the main surface of the substrate exposed by forming the contact hole.
    Type: Grant
    Filed: April 4, 2013
    Date of Patent: November 3, 2015
    Assignees: Sumitomo Electric Industries, Ltd., Renesas Electronics Corporation
    Inventors: Taku Horii, Shinji Kimura, Mitsuo Kimoto
  • Publication number: 20150171170
    Abstract: A first impurity region is formed by ion implantation of a first impurity into a first main surface of a silicon carbide substrate. A metal layer is formed in contact with the first impurity region. By annealing the silicon carbide substrate and the metal layer, an electrode is formed. The metal layer is formed such that a concentration of a first impurity at a boundary portion between the metal layer and the first impurity region becomes less than a maximum value of a concentration of the first impurity in the first impurity region. The electrode is formed such that a concentration of the first impurity at a boundary portion between the electrode and the first impurity region becomes not less than 80% of a maximum value of a concentration of the first impurity in the first impurity region in a normal direction.
    Type: Application
    Filed: November 21, 2014
    Publication date: June 18, 2015
    Inventors: Shunsuke YAMADA, So TANAKA, Ryosuke KUBOTA, Taku HORII
  • Patent number: 9048093
    Abstract: A single crystal substrate made of silicon carbide and a first support substrate having a size greater than a size of each of the single crystal substrates are prepared. The single crystal substrate is bonded onto the first support substrate. Process on the single crystal substrate bonded to the first support substrate is performed. The first support substrate is removed. The single crystal substrate is subjected to heat treatment. The single crystal substrate is bonded onto a second support substrate having a size greater than the size of the single crystal substrate. Process on the single crystal substrate bonded to the second support substrate is performed.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: June 2, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Taku Horii
  • Patent number: 8916462
    Abstract: A method for manufacturing a MOSFET includes the steps of: preparing a substrate made of silicon carbide; forming a drain electrode making ohmic contact with the substrate; and forming a backside pad electrode on and in contact with the drain electrode. The drain electrode formed in the step of forming the drain electrode is made of an alloy containing Ti and Si. Further, the backside pad electrode formed is maintained at a temperature of 300° C. or smaller until completion of the MOSFET. Accordingly, the manufacturing process can be efficient while achieving excellent adhesion between the electrodes.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: December 23, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hiroyuki Kitabayashi, Hideto Tamaso, Taku Horii
  • Patent number: 8901698
    Abstract: A method for manufacturing a Schottky barrier diode includes the following steps. First, a GaN substrate is prepared. A GaN layer is formed on the GaN substrate. A Schottky electrode including a first layer made of Ni or Ni alloy and in contact with the GaN layer is formed. The step of forming the Schottky electrode includes a step of forming a metal layer to serve as the Schottky electrode and a step of heat treating the metal layer. A region of the GaN layer in contact with the Schottky electrode has a dislocation density of 1×108 cm?2 or less.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: December 2, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Taku Horii, Tomihito Miyazaki, Makoto Kiyama
  • Patent number: 8815716
    Abstract: A semiconductor device includes a semiconductor layer (1) containing GaN and an electrode. The electrode includes an electrode main body (6), a connection-use electrode (8) containing Al and formed at a position farther from the semiconductor layer (1) than the electrode main body (6), and a barrier layer (7) formed between the electrode main body (6) and the connection-use electrode (8), the barrier layer (7) containing at least one selected from the group consisting of W, TiW, WN, TiN, Ta, and TaN. A surface roughness RMS of the barrier layer (7) is 3.0 nm or less.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: August 26, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Tomihito Miyazaki, Makoto Kiyama, Taku Horii
  • Patent number: 8802552
    Abstract: A method for manufacturing a MOSFET includes the steps of: forming a gate oxide film on an active layer, forming a gate electrode on the gate oxide film, forming a source contact electrode in ohmic contact with the active layer, and forming an interlayer insulating film made of silicon dioxide so as to cover the gate electrode after the source contact electrode is formed. The step of forming a source contact electrode includes the steps of forming a metal layer including aluminum so as to be in contact with the active layer, and alloying the metal layer.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: August 12, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Taku Horii, Takeyoshi Masuda
  • Publication number: 20140103365
    Abstract: A semiconductor device includes: a substrate made of silicon carbide; an insulating film formed on a surface of the substrate; a buffer film containing no Al; and an electrode containing Al. The substrate has an electrically conductive region. In the semiconductor device, a contact hole is formed above the electrically conductive region so as to extend through the insulating film and expose the surface of the substrate. The buffer film extends upward on a side wall surface of the contact hole from a bottom surface of the contact hole. The electrode is formed in contact with the electrically conductive region on the bottom surface of the contact hole, and is formed on the insulating film with the buffer film being interposed therebetween.
    Type: Application
    Filed: October 11, 2013
    Publication date: April 17, 2014
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Kazunori Fujimoto, Taku Horii, Shinji Kimura, Mitsuo Kimoto
  • Publication number: 20140080292
    Abstract: A semiconductor device includes a semiconductor layer (1) containing GaN and an electrode. The electrode includes an electrode main body (6), a connection-use electrode (8) containing Al and formed at a position farther from the semiconductor layer (1) than the electrode main body (6), and a barrier layer (7) formed between the electrode main body (6) and the connection-use electrode (8), the barrier layer (7) containing at least one selected from the group consisting of W, TiW, WN, TiN, Ta, and TaN. A surface roughness RMS of the barrier layer (7) is 3.0 nm or less.
    Type: Application
    Filed: November 19, 2013
    Publication date: March 20, 2014
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Tomihito Miyazaki, Makoto Kiyama, Taku HORII
  • Patent number: 8614446
    Abstract: A semiconductor device includes a semiconductor layer (1) containing GaN and an electrode. The electrode includes an electrode main body (6), a connection-use electrode (8) containing Al and formed at a position farther from the semiconductor layer (1) than the electrode main body (6), and a barrier layer (7) formed between the electrode main body (6) and the connection-use electrode (8), the barrier layer (7) containing at least one selected from the group consisting of W, TiW, WN, TiN, Ta, and TaN. A surface roughness RMS of the barrier layer (7) is 3.0 nm or less.
    Type: Grant
    Filed: December 25, 2009
    Date of Patent: December 24, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Tomihito Miyazaki, Makoto Kiyama, Taku Horii
  • Patent number: 8609513
    Abstract: A method for manufacturing a semiconductor device includes the steps of: preparing a combined wafer; obtaining a first intermediate wafer by forming an active layer; obtaining a second intermediate wafer by forming a front-side electrode on the first intermediate wafer; supporting the second intermediate wafer by adhering an adhesive tape at the front-side electrode side; removing the supporting layer while supporting the second intermediate wafer using the adhesive tape; forming a backside electrode on the main surfaces of SiC substrates exposed by the removal of the supporting layer; adhering an adhesive tape at the backside electrode side and removing the adhesive tape at the front-side electrode side so as to support the plurality of SiC substrates using the adhesive tape; and obtaining a plurality of semiconductor devices by cutting the SiC substrates with the SiC substrates being supported by the adhesive tape provided at the backside electrode side.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: December 17, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Taku Horii
  • Patent number: 8581359
    Abstract: A Schottky barrier diode includes a GaN freestanding substrate having a front surface, a GaN epitaxial layer deposited on the front surface, and an insulation layer deposited on the GaN epitaxial layer at a front surface and having an opening. Furthermore, the Schottky barrier diode also includes an electrode. The electrode is configured by a Schottky electrode provided in the opening in contact with the GaN epitaxial layer, and a field plate electrode connected to the Schottky electrode and also overlapping the insulation layer. The GaN freestanding substrate has a dislocation density of at most 1×108 cm?2.
    Type: Grant
    Filed: August 22, 2008
    Date of Patent: November 12, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Taku Horii, Tomihito Miyazaki, Makoto Kiyama
  • Publication number: 20130292695
    Abstract: A method for manufacturing a Schottky barrier diode includes the following steps. First, a GaN substrate is prepared. A GaN layer is formed on the GaN substrate. A Schottky electrode including a first layer made of Ni or Ni alloy and in contact with the GaN layer is formed. The step of forming the Schottky electrode includes a step of forming a metal layer to serve as the Schottky electrode and a step of heat treating the metal layer. A region of the GaN layer in contact with the Schottky electrode has a dislocation density of 1×108 cm?2 or less.
    Type: Application
    Filed: July 3, 2013
    Publication date: November 7, 2013
    Inventors: Taku HORII, Tomihito Miyazaki, Makato Kiyama
  • Publication number: 20130292703
    Abstract: A MOSFET includes: a substrate; a gate insulating film; a gate electrode; an interlayer insulating film formed on the gate insulating film to surround the gate electrode; a buffer film containing Ti and N and containing no Al; and a source electrode containing Ti, Al, and Si. In the MOSFET, a contact hole is formed away from the gate electrode so as to extend through the interlayer insulating film and expose a main surface of the substrate. The buffer film is formed in contact with a side wall surface of the contact hole. The source electrode is formed on and in contact with the buffer film and the main surface of the substrate exposed by forming the contact hole.
    Type: Application
    Filed: April 4, 2013
    Publication date: November 7, 2013
    Applicants: Renesas Electronics Corporation, Sumitomo Electric Industries, Ltd.
    Inventors: Taku HORII, Shinji Kimura, Mitsuo Kimoto
  • Publication number: 20130292702
    Abstract: A semiconductor device includes a substrate, a gate insulating film, a gate electrode, an interlayer insulating film, and a buffer film containing Ti and N and containing no Al, and a source electrode containing Ti, Al, and Si. In the semiconductor device, a contact hole is formed away from the gate electrode so as to extend through the interlayer insulating film. The gate insulating film is formed on a main surface of the substrate, which is formed of a plane having an off angle of not less than 50° and not more than 65° relative to a {0001} plane. The buffer film is formed in contact with a side wall surface of the contact hole. The source electrode is formed on and in contact with the buffer film and the main surface of the substrate.
    Type: Application
    Filed: April 4, 2013
    Publication date: November 7, 2013
    Applicant: Sumitomo Electric Industries, Ltd
    Inventor: Taku HORII
  • Publication number: 20130252400
    Abstract: A single crystal substrate made of silicon carbide and a first support substrate having a size greater than a size of each of the single crystal substrates are prepared. The single crystal substrate is bonded onto the first support substrate. Process on the single crystal substrate bonded to the first support substrate is performed. The first support substrate is removed. The single crystal substrate is subjected to heat treatment. The single crystal substrate is bonded onto a second support substrate having a size greater than the size of the single crystal substrate. Process on the single crystal substrate bonded to the second support substrate is performed.
    Type: Application
    Filed: February 14, 2013
    Publication date: September 26, 2013
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventor: Taku Horii
  • Patent number: 8502337
    Abstract: A method for manufacturing a Schottky barrier diode includes the following steps. First, a GaN substrate is prepared. A GaN layer is formed on the GaN substrate. A Schottky electrode including a first layer made of Ni or Ni alloy and in contact with the GaN layer is formed. The step of forming the Schottky electrode includes a step of forming a metal layer to serve as the Schottky electrode and a step of heat treating the metal layer. A region of the GaN layer in contact with the Schottky electrode has a dislocation density of 1×108 cm?2 or less.
    Type: Grant
    Filed: July 23, 2009
    Date of Patent: August 6, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Taku Horii, Tomihito Miyazaki, Makoto Kiyama
  • Publication number: 20130143398
    Abstract: A method for manufacturing a MOSFET includes the steps of: preparing a substrate made of silicon carbide; forming a drain electrode making ohmic contact with the substrate; and forming a backside pad electrode on and in contact with the drain electrode. The drain electrode formed in the step of forming the drain electrode is made of an alloy containing Ti and Si. Further, the backside pad electrode formed is maintained at a temperature of 300° C. or smaller until completion of the MOSFET. Accordingly, the manufacturing process can be efficient while achieving excellent adhesion between the electrodes.
    Type: Application
    Filed: September 11, 2012
    Publication date: June 6, 2013
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Hiroyuki Kitabayashi, Hideto Tamaso, Taku Horii