Patents by Inventor Takuji Maeda

Takuji Maeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110202752
    Abstract: A secure LSI device 1 includes an encryption section 2 for encrypting a program, and an external I/F 50 for inputting/outputting a program or data from/to an external memory 100. In the encryption section 2, the operation of a private key arithmetic processing section 20 is prohibited with respect to a sequence whose execution is determined by a key-generation/update sequencer 30 to be impermissible. In the external I/F 50, a program processing section 51 and a data processing section 55 are structured independently from each other.
    Type: Application
    Filed: April 21, 2011
    Publication date: August 18, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Makoto FUJIWARA, Yusuke Nemoto, Junichi Yasui, Takuji Maeda, Takayuki Ito, Yasushi Yamada, Shinji Inoue
  • Publication number: 20110188866
    Abstract: A coherent optical communication device includes a demodulator configured to demodulate a reception signal; a local oscillator light optical source configured to generate local oscillator light used for demodulating the reception signal; a memory configured to store wavelength information; and a controller configured to control the local oscillator light optical source when the demodulator cannot receive the reception signal, so that a wavelength of the local oscillator light generated in the local oscillator light optical source is changed to a wavelength specified by the wavelength information stored in the memory.
    Type: Application
    Filed: January 25, 2011
    Publication date: August 4, 2011
    Applicant: FUJITSU LIMITED
    Inventor: Takuji MAEDA
  • Patent number: 7984231
    Abstract: When moving image data or the like is recorded into an information recording medium, such as a flash memory, in real time, an influence of locations of free recording areas upon the recording speed is suppressed to ensure the real time performance of the data recording. In an access apparatus, there is provided an area management block control part that manages FAT1 and FAT2, which are area management information of a nonvolatile memory, on a FAT block-by-FAT block basis, and the length of the free recording area in each FAT block is calculated. Then, area management block information, in which the free recording area length in each FAT block is recorded, is generated on a RAM. A FAT block in which the free recording area length exceeds a threshold value is assigned to the data recording, thereby suppressing the number of updates of the area management information regardless of the location of the free areas.
    Type: Grant
    Filed: September 12, 2006
    Date of Patent: July 19, 2011
    Assignee: Panasonic Corporation
    Inventors: Takuji Maeda, Shinji Inoue
  • Publication number: 20110125928
    Abstract: A host device is connected to a storage device via a bus and reads and writes data in the storage device. The host device includes a command transmitter that sequentially transmits a command in a command sequence, which includes a set of commands which do not change data stored in the storage device, and a response receptor that accepts a response from the storage device for each command transmission from the command transmitter and determines whether or not an error exists. An acceptable/unacceptable access determiner provided in the host device enables access to the storage device when a normal response is identified by the response receptor and otherwise determines that access to the storage device is unacceptable. The normal response is when the responses received from the storage device for the transmissions of all commands in the command sequence do not include an error.
    Type: Application
    Filed: January 27, 2011
    Publication date: May 26, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Masayuki TOYAMA, Takuji MAEDA, Tomoaki IZUMI, Shouichi TSUJITA, Masahiro NAKANISHI, Shinji INOUE
  • Publication number: 20110125958
    Abstract: A predetermined number of erasable blocks positioned at a start of a volume area in a semiconductor memory card are provided so as to include volume management information. A user area following the volume management information includes a plurality of clusters. A data length NOM of an area from a master boot record & partition table sector to a partition boot sector is determined so that the plurality of clusters in the user area are not arranged so as to straddle erasable block boundaries. Since cluster boundaries and erasable block boundaries in the user area are aligned, there is no need to perform wasteful processing in which two erasable blocks are erased to rewrite one cluster.
    Type: Application
    Filed: January 25, 2011
    Publication date: May 26, 2011
    Inventors: Takuji MAEDA, Teruto Hirota
  • Patent number: 7930501
    Abstract: Each of memory cards can have a different type and can be in a plurality of statuses. The memory cards are managed by a file system and data is read/written from/to the memory cards via an access device. Each of the memory cards has a recording area in which data is recorded and managed by an independent file system, a state storage section for storing state assigned to each of combinations of the memory card type and status and being capable of uniquely identifying the combination, and card information storage sections the number of which is identical to the number of states the memory card can have, and which store physical characteristics concerning the recording area. The access device acquires from the memory card a state enable uniquely identifying the memory card type and status. According to the state acquired, the access device identifies the type and status of the memory card and executes processing in accordance with the memory card state.
    Type: Grant
    Filed: April 18, 2005
    Date of Patent: April 19, 2011
    Assignee: Panasonic Corporation
    Inventors: Takuji Maeda, Hirokazu So, Shinji Inoue
  • Patent number: 7921229
    Abstract: A host device (1) adds host function information indicating a function of the host device (1) to a command and transmits it to a storage device (2). The storage device (2) receives the command transmitted from the host device (1) and determines whether the function indicated by the host function information can be processed. When the function can be processed, the function is processed based on the command. When the function cannot be processed, no response is returned or error information is returned. Thus, under simple control, it is possible to prevent data destruction by a host device of an old version.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: April 5, 2011
    Assignee: Panasonic Corporation
    Inventors: Masayuki Toyama, Takuji Maeda, Tomoaki Izumi, Shouichi Tsujita, Masahiro Nakanishi, Shinji Inoue
  • Publication number: 20110055297
    Abstract: A method for increasing the speed of processing when writing multiple files in parallel and writing file data in a stable manner in the case where the regions of a non-volatile memory in an information recording module are managed according to a filesystem is provided. An access module (1) includes a unit (104) that communicates, to an information recording module (2), information regarding the storage location of a directory entry, and also includes a unit (105) that pads file data when writing fractional data such as the end of a file and writes that data into the information recording module (2). Upon determining that the directory entry is to be written based on the communicated information, the information recording module (2) stores the directory entry in a dedicated physical block. Furthermore, the access module (1) pads the data of multiple files as necessary and records those files in continuous addresses in units that are a multiple of a predetermined size of a unit of recording processing.
    Type: Application
    Filed: March 4, 2010
    Publication date: March 3, 2011
    Inventors: Takuji Maeda, Masayuki Toyama, Manabu Inoue, Toshiyuki Honda
  • Publication number: 20110055467
    Abstract: Area management information is cached in a cache memory by controlling the access size when an information processor accesses the area management information in an information recording medium. When the processing content of the information processor is to retrieve a free area from the area management information, a physical management block size determined from the physical characteristics of the information recording medium is used. When the processing content is to acquire a link destination from the area management information, minimum access unit of the information recording medium is used. Consequently, overhead can be lessened when the area management information is accessed.
    Type: Application
    Filed: November 9, 2010
    Publication date: March 3, 2011
    Inventors: Takuji MAEDA, Masato Suto, Hirokazu So, Makoto Ochi, Shinji Inoue
  • Patent number: 7899982
    Abstract: A predetermined number of erasable blocks positioned at a start of a volume area in a semiconductor memory card are provided so as to include volume management information. A user area following the volume management information includes a plurality of clusters. A data length NOM of an area from a master boot record & partition table sector to a partition boot sector is determined so that the plurality of clusters in the user area are not arranged so as to straddle erasable block boundaries. Since cluster boundaries and erasable block boundaries in the user area are aligned, there is no need to perform wasteful processing in which two erasable blocks are erased to rewrite one cluster.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: March 1, 2011
    Assignee: Panasonic Corporation
    Inventors: Takuji Maeda, Teruto Hirota
  • Patent number: 7900007
    Abstract: A host device transmits a command from a command transmission unit (101a) along a predetermined command sequence. A storage device (2) receives the command in a command reception unit (202a). An access determination unit (202c) determines the sequence of the command transmitted from the host device (1) and determines that reception of the access to the host device (1) is enabled only when the sequence is identical with a predetermined sequence. Thus, with simple control, it is possible to prevent data destruction by a host device of an old version.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: March 1, 2011
    Assignee: Panasonic Corporation
    Inventors: Masayuki Toyama, Takuji Maeda, Tomoaki Izumi, Shouichi Tsujita, Masahiro Nakanishi, Shinji Inoue
  • Publication number: 20110022807
    Abstract: An access device 1 internally includes a logical-physical empty capacity management part 16 for obtaining information of a remaining capacity on a write once memory from a write once recording device 2A. In addition, the write once recording device 2A internally includes a physical empty capacity management part 27 for managing a remaining capacity on the write once memory and notifying the access device of the capacity. Prior to recording of file data, the access device 1 can know an accurate remaining capacity of the write once recording device by: obtaining a remaining capacity of the write once memory from the write once recording device 2A; and comparing the capacity with a remaining capacity on an FAT to decide an actually-recordable remaining capacity for file data.
    Type: Application
    Filed: December 10, 2007
    Publication date: January 27, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Takuji Maeda, Shinji Inoue, Hiroki Etoh, Masahiro Nakamura, Makoto Ochi, Yukiko Okamoto, Masahiro Nakanishi
  • Publication number: 20110022645
    Abstract: An information recording device, which includes a nonvolatile memory whose areas are managed using an FAT file system and enhances the reliability of directory entries using a cyclic shift checksum, recalculates the cyclic shift checksum efficiently and performs seeking at a higher speed. A nonvolatile memory (25) of an information recording device 2 is managed using an FAT file system. In the memory, a plurality of directory entries are allocated to a single file. The device enhances the reliability of the directory entries using a cyclic shift checksum, and manages information indicating the position and the size of a storage area of file data using an extent information entry (203). The device further uses an update information entry (204) and a dummy entry (205).
    Type: Application
    Filed: April 1, 2009
    Publication date: January 27, 2011
    Inventors: Takuji Maeda, Shinji Inoue
  • Publication number: 20100329456
    Abstract: A secure LSI device 1 includes an encryption section 2 for encrypting a program, and an external I/F 50 for inputting/outputting a program or data from/to an external memory 100. In the encryption section 2, the operation of a private key arithmetic processing section 20 is prohibited with respect to a sequence whose execution is determined by a key-generation/update sequencer 30 to be impermissible. In the external I/F 50, a program processing section 51 and a data processing section 55 are structured independently from each other.
    Type: Application
    Filed: September 8, 2010
    Publication date: December 30, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Makoto FUJIWARA, Yusuke NEMOTO, Junichi YASUI, Takuji MAEDA, Takayuki ITO, Yasushi YAMADA, Shinji INOUE
  • Publication number: 20100332717
    Abstract: Provided is a method that, in the case of managing areas of a non-volatile memory of an information recording module by a file system, increases the speed of processing for writing file data and file system management information, and furthermore prevents a decrease in the rewriting lifetime of the non-volatile memory. The information recording module (2) is provided with a page cache control unit (217) that stores page cache information (224) in the non-volatile memory (22) of the information recording module (2) and performs control such that a specific physical block is used as a cache when writing small-sized data. Also, an access module (1) is provided with a page cache information setting unit (104) that sets information necessary for page cache control in the information recording module (2).
    Type: Application
    Filed: February 27, 2009
    Publication date: December 30, 2010
    Inventors: Takuji Maeda, Shigekazu Kogita, Shinji Inoue, Hiroki Etoh, Makoto Ochi, Masahiro Nakamura
  • Publication number: 20100315702
    Abstract: An optical transmission node including an optical preamplifier to amplify input light and an optical postamplifier to amplify light output from the optical preamplifier, includes the optical postamplifier configured to generate amplified spontaneous emission light without signals input, the optical preamplifier configured to amplify the amplified spontaneous emission light from the optical postamplifier, a loopback switch configured to discouple a path of the light output from the optical preamplifier to the optical postamplifier, and couple a path of the light output from the optical postamplifier to the optical preamplifier.
    Type: Application
    Filed: June 15, 2010
    Publication date: December 16, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Hiroyuki ITOH, Takuji Maeda
  • Patent number: 7849331
    Abstract: A system including a secure LSI 1 establishes a communication path to/from a server 3 (UD1), and receives a common key-encrypted program generated by encryption with a common key and transmitted from the server 3 (UD6 and UD7). The received common key-encrypted program is decrypted to generate a raw program, and the raw program is re-encrypted with an inherent key to newly generate an inherent key-encrypted program, which is stored in an external memory.
    Type: Grant
    Filed: April 23, 2008
    Date of Patent: December 7, 2010
    Assignee: Panasonic Corporation
    Inventors: Makoto Fujiwara, Yusuke Nemoto, Junichi Yasui, Takuji Maeda, Takayuki Ito, Yasushi Yamada, Shinji Inoue
  • Patent number: 7840729
    Abstract: A semiconductor memory card (101) has a plurality of areas (105, 106) based on different file systems. An adapter (102) includes: an area switching part (110) which a user can operates, a determination part (109) for determining the operation; and a card controller (108) for issuing a switching command for switching the area to be used for the semiconductor memory card (101) in accordance with the judgment result. When the switching command is issued in response to input from the area switching part (110), the command is interpreted by an area selector (107) of the semiconductor memory card (101) so as to select an area.
    Type: Grant
    Filed: November 18, 2004
    Date of Patent: November 23, 2010
    Assignee: Panasonic Corporation
    Inventors: Shinji Inoue, Kazuya Fujimura, Yukiko Inoue, Takuji Maeda, Makoto Ochi, Masato Suto, Hirokazu So
  • Patent number: 7840749
    Abstract: Area management information is cached in a cache memory by controlling the access size when an information processor accesses the area management information in an information recording medium. When the processing content of the information processor is to retrieve a free area from the area management information, a physical management block size determined from the physical characteristics of the information recording medium is used. When the processing content is to acquire a link destination from the area management information, minimum access unit of the information recording medium is used. Consequently, overhead can be lessened when the area management information is accessed.
    Type: Grant
    Filed: July 13, 2004
    Date of Patent: November 23, 2010
    Assignee: Panasonic Corporation
    Inventors: Takuji Maeda, Masato Suto, Hirokazu So, Makoto Ochi, Shinji Inoue
  • Patent number: 7831841
    Abstract: A secure LSI device 1 includes an encryption section 2 for encrypting a program, and an external I/F 50 for inputting/outputting a program or data from/to an external memory 100. In the encryption section 2, the operation of a private key arithmetic processing section 20 is prohibited with respect to a sequence whose execution is determined by a key-generation/update sequencer 30 to be impermissible. In the external I/F 50, a program processing section 51 and a data processing section 55 are structured independently from each other.
    Type: Grant
    Filed: January 22, 2008
    Date of Patent: November 9, 2010
    Assignee: Panasonic Corporation
    Inventors: Makoto Fujiwara, Yusuke Nemoto, Junichi Yasui, Takuji Maeda, Takayuki Ito, Yasushi Yamada, Shinji Inoue