Abstract: A method for manufacturing a semiconductor device having a trench gate is provided. The method includes the steps of: forming a trench in a substrate, the trench having a depth equal to or deeper than 10 &mgr;m; annealing the substrate in a reducing atmosphere; and forming a gate insulation film on an inner wall of the trench. The substrate is annealed at a temperature between 950° C. and 1030° C. under a pressure of the reducing atmosphere equal to or higher than 20 kPa in the step of annealing. The semiconductor device includes a transistor having excellent properties. Specifically, a threshold voltage of the transistor is substantially uniformed, a gate oxide film of the transistor is not deteriorated, and crystal defects near the trench are reduced.

Abstract: A method is provided for manufacturing a MONOS type non-volatile memory device. The method comprises the following steps: a step of pattering a stopper layer and a first conductive layer; a step of forming an ONO film composed of a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer above a semiconductor substrate and on both sides of the first conductive layer; a step of forming a second conductive layer above the ONO film 220; a step of anisotropically etching the second conductive layer, and then isotropically etching the same, thereby forming control gates in the form of sidewalls through the ONO films on both side surfaces of the first conductive layer; and a step of patterning the first conductive layer to form a word gate.

Abstract: A method for manufacturing a semiconductor device in accordance with an embodiment of the present invention includes a step of forming a TiN film 2 on an underlying film 1; a step of coating a photoresist film on the TiN film 2, and exposing and developing the photoresist film; a step of etching the TiN film 2 using the photoresist film 4a as a mask, by using an etching apparatus that etches an Al alloy film; a step of introducing a mixed gas containing O2 gas and N2 gas adjacent to the photoresist film, and plasmatizing the gas to thereby ash the photoresist film, and a step of introducing H2O gas adjacent to the TiN film, and plasmatizing the gas to thereby ash foreign matter on the TiN film.

Abstract: It is an object to provide a blade member for an airplane which is simple in structure, and moreover is excellent with respects to weight, aerodynamic performance, cost, strength and durability. A vane of a double-slotted flap includes: an outer skin area surrounded by a first outer skin, a second outer skin, a leading edge and a trailing edge each having a predetermined wall thickness. Front and rear reinforcing areas are provided that extend in a span direction within the outer skin area and are connected to the first outer skin and the second outer skin. The outer skin area and the reinforcing areas are integrally formed by wire electrical discharge-machining. The first outer skin and the second outer skin respectively have thickened portions thicker than the other portions, and the trailing edge is formed to have a thickness which is approximately zero. This blade member can be simplified in structure, leading to reductions in the number of parts, number of assembling steps and weight.

Abstract: A method for manufacturing a semiconductor device in accordance with an embodiment of the present invention includes a step of forming a TiN film 2 on an underlying film 1; a step of coating a photoresist film on the TiN film 2, and exposing and developing the photoresist film; a step of etching the TiN film 2 using the photoresist film 4a as a mask, by using an etching apparatus that etches an Al alloy film; a step of introducing a mixed gas containing O2 gas and N2 gas adjacent to the photoresist film, and plasmatizing the gas to thereby ash the photoresist film, and a step of introducing H2O gas adjacent to the TiN film, and plasmatizing the gas to thereby ash foreign matters on the TiN film.

Abstract: In a semiconductor device, a p-type base region is provided in an n−-type substrate to extend from a principal surface of the substrate in a perpendicular direction to the principal surface. An n+-type source region extends in the p-type base region from the principal surface in the perpendicular direction, and an n+-type drain region extends in the substrate separately from the p-type base region with a drift region interposed therebetween. A trench is formed to penetrate the p-type base region from the n+-type source region in a direction parallel to the principal surface. A gate electrode is formed in the trench through a gate insulating film. Accordingly, a channel region can be formed with a channel width in a depth direction of the trench when a voltage is applied to the gate electrode.

Abstract: A method, for manufacturing a nonvolatile memory device, includes: forming a gate layer above which a stopper layer is disposed on a semiconductor layer; forming control gates on both side surfaces of the gate layer with an ONO film interposed therebetween; forming an insulating layer over the entire surface; polishing the insulating layer so that the stopper layer is exposed; removing the stopper layer and thereby exposing the top surface of the gate layer; forming a conductive layer above the gate layer and the insulating layer; etching the conductive layer and the gate layer and thereby forming a word line and a word gate and removing the gate layer remained under the etching.

Abstract: A method is provided for manufacturing a MONOS type non-volatile memory device. The method comprises the following steps: a step of pattering a stopper layer and a first conductive layer; a step of forming an ONO film composed of a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer above a semiconductor substrate and on both sides of the first conductive layer; a step of forming a second conductive layer above the ONO film 220; a step of anisotropically etching the second conductive layer, and then isotropically etching the same, thereby forming control gates in the form of sidewalls through the ONO films on both side surfaces of the first conductive layer; and a step of patterning the first conductive layer to form a word gate.

Abstract: A method is provided for manufacturing a MONOS type non-volatile memory device. The method comprises the following steps: a step of pattering a stopper layer, a first silicon oxide layer and a first conductive layer; a step of forming an ONO film; a step of forming a second conductive layer above the ONO film; a step of anisotropically etching the second conductive layer to form control gates on both side surfaces of the first conductive layer through the ONO film, a step of forming a second silicon oxide layer over the entire surface; a step of polishing the second silicon oxide layer in a manner to expose the stopper layer; a step of removing the stopper layer by dry etching; a step of removing the first silicon oxide layer; and a step of patterning the first conductive layer to form a word gate.

Abstract: The manufacturing method of the invention performs over etching to remove an upper portion of a conductive layer in a logic circuit area of a semiconductor device, simultaneously with etching out a stopper layer. The method subsequently patterns the conductive layer to form gate electrodes in the logic circuit area. The height of the gate electrodes is lowered, because of the removed upper portion of the conductive layer. In a subsequent process of polishing an insulating layer, even when the polishing rate of the insulating layer is not constant but varied and the insulating layer in the logic circuit area is polished relatively faster than the insulating layer in a memory area, this arrangement of the invention effectively prevents exposure of the gate electrodes in the logic circuit area, prior to exposure of stopper layers in the memory area.

Abstract: A method, for manufacturing a nonvolatile memory device, includes: forming a first insulating layer above a semiconductor layer; forming a first conductive layer above the first insulating layer: forming a stopper layer above the first conductive layer; patterning the stopper layer and the first conductive layer; forming an ONO film made of a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer above the semiconductor layer and on both side surfaces of the first conductive layer; forming a second conductive layer above the ONO film; applying anisotropic etching to the second conductive layer, and thereby forming a side wall-like control gate aside each of both side surfaces of the first conductive layer, the ONO film being interposed therebetween; forming an impurity layer to be a source region or a drain region inside of the semiconductor layer; forming a second insulating layer over an entire surface; polishing the second insulating layer so as to expose the stopper layer; rem

Abstract: In a trench-gate type power MOSFET in which a gate electrode is formed on a gate oxide layer formed on a surface of a wall defining a trench, the trench is annealed by heating, for example, at the temperature between 1050° C. and 1150° C. in a hydrogen atmosphere before the gate oxide layer is formed. The crystal defects generated in a crystal adjacent to the trench are cured by the hydrogen annealing without enlarging the trench horizontal width, so that a trench having a high aspect ratio is provided while leak current at a PN junction is prevented. In addition, the breakdown voltage of the gate oxide layer is prevented from being lowered.

Abstract: The manufacturing method of the invention performs over-etching to remove an upper portion of a conductive layer in a logic circuit area of a semiconductor device, simultaneously with etching out a stopper layer. The method subsequently patterns the conductive layer to form gate electrodes in the logic circuit area. The height of the gate electrodes is lowered, because of the removed upper portion of the conductive layer. In a subsequent process of polishing an insulating layer, even when the polishing rate of the insulating layer is not constant but varied and the insulating layer in the logic circuit area is polished relatively faster than the insulating layer in a memory area, this arrangement of the invention effectively prevents exposure of the gate electrodes in the logic circuit area, prior to exposure of stopper layers in the memory area.

Abstract: In a semiconductor device, a p-type base region is provided in an n−-type substrate to extend from a principal surface of the substrate in a perpendicular direction to the principal surface. An n+-type source region extends in the p-type base region from the principal surface in the perpendicular direction, and an n+-type drain region extends in the substrate separately from the p-type base region with a drift region interposed therebetween. A trench is formed to penetrate the p-type base region from the n+-type source region in a direction parallel to the principal surface. A gate electrode is formed in the trench through a gate insulating film. Accordingly, a channel region can be formed with a channel width in a depth direction of the trench when a voltage is applied to the gate electrode.

Abstract: A semiconductor device manufacturing method forms precision device isolation areas of a desirable minimum feature size in a semiconductor device having trench isolation areas. Steps include: (a) forming a polishing stopper layer 140 having a specific pattern on a semiconductor substrate 10; (b) forming trenches 16 in the semiconductor substrate 10 by etching using at least the polishing stopper layer 140 as a mask; (c) forming a protective layer 18 on the trench 16 surfaces; (d) causing the position of an edge part of the polishing stopper layer 14 to recede from the position of the trench 16 sidewalls; (e) forming an insulation layer 21 on the semiconductor substrate 10 so as to fill the trenches 16; and (f) forming trench isolation areas 30 by polishing the insulation layer 21 using the polishing stopper layer 14 as a stopper.

Abstract: A method for manufacturing a semiconductor device in accordance with an embodiment of the present invention includes a step of forming a TiN film 2 on an underlying film 1; a step of coating a photoresist film on the TiN film 2, and exposing and developing the photoresist film; a step of etching the TiN film 2 using the photoresist film 4a as a mask, by using an etching apparatus that etches an Al alloy film; a step of introducing a mixed gas containing O2 gas and N2 gas adjacent to the photoresist film, and plasmatizing the gas to thereby ash the photoresist film, and a step of introducing H2O gas adjacent to the TiN film, and plasmatizing the gas to thereby ash foreign matters on the TiN film.

Abstract: In a semiconductor device, a p-type base region is provided in an n−-type substrate to extend from a principal surface of the substrate in a perpendicular direction to the principal surface. An n+-type source region extends in the p-type base region from the principal surface in the perpendicular direction, and an n+-type drain region extends in the substrate separately from the p-type base region with a drift region interposed therebetween. A trench is formed to penetrate the p-type base region from the n+-type source region in a direction parallel to the principal surface. A gate electrode is formed in the trench through a gate insulating film. Accordingly, a channel region can be formed with a channel width in a depth direction of the trench when a voltage is applied to the gate electrode.

Abstract: A semiconductor device has a dielectric strength for a gate oxide film at a trench bottom that is higher than that of side walls used for channels. An n+0 type substrate 1 having substrate plane orientation of (110) is prepared, and the side walls of a trench where channels are formed are in (100) planes. The other, non-channel forming, side walls of the trench are in (110) planes. Thus, the growth rate of the gate oxide film 7 in the non-channel forming side walls and the trench bottom is faster than that in the channel forming side walls. As a result, the film thickness at the non-channel-forming side walls and the trench bottom is greater than that of the channel-forming side walls. Accordingly, the device has high mobility, and there is no drop of dielectric strength due to partial reduction of the thickness of the gate oxide film 7. This achieves both a reduction of the ON resistance and an increase in the dielectric strength of the semiconductor device.

Abstract: A semiconductor device has a dielectric strength for a gate oxide film at a trench bottom that is higher than that of side walls used for channels. An n+ type substrate 1 having substrate plane orientation of (110) is prepared, and the side walls of a trench where channels are formed are in (100) planes. The other, non-channel forming, side walls of the trench are in (110) planes. Thus, the growth rate of the gate oxide film 7 in the non-channel forming side walls and the trench bottom is faster than that in the channel forming side walls. As a result, the film thickness at the non-channel-forming side walls and the trench bottom is greater than that of the channel-forming side walls. Accordingly, the device has high mobility, and there is no drop of dielectric strength due to partial reduction of the thickness of the gate oxide film 7. This achieves both a reduction of the ON resistance and an increase in the dielectric strength of the semiconductor device.

Abstract: In a trench-gate type power MOSFET in which a gate electrode is formed on a gate oxide layer formed on a surface of a wall defining a trench, the trench is annealed by heating, for example, at the temperature between 1050° C. and 1150° C. in a hydrogen atmosphere before the gate oxide layer is formed. The crystal defects generated in a crystal adjacent to the trench are cured by the hydrogen annealing without enlarging the trench horizontal width, so that a trench having a high aspect ratio is provided while leak current at a PN junction is prevented. In addition, the breakdown voltage of the gate oxide layer is prevented from being lowered.