Abstract: A random work arranging device that arranges randomly conveyed works by using a robot and carries out the arranged works, wherein the robot comprises a plurality of arms and a single robot controller for controlling respective arms independently one another to arrange and transfer the works from a conveying position to a carry-out position.

Abstract: A method of fabricating a semiconductor device having, for example, a memory cell array portion and a peripheral circuit portion is disclosed. By such a method, a first interlayer insulating film is formed on a semiconductor substrate, a first connection hole is formed by selectively removing a predetermined portion of the first interlayer insulating film, the sides of the first hole being substantially vertical to the bottom thereof, a first plug is formed by padding the first hole with a metallic film and, subsequently, a second interlayer insulating film is formed on the first insulating film, a second hole is formed by selectively removing a predetermined portion of the second interlayer insulating film, the sides of the second hole being substantially vertical to the bottom thereof, and a second plug aligned to be in direct connection with the first plug is formed by padding the second hole with the metallic film.

Abstract: In order to improve connection reliability of a feeding interconnection connected to an electrode of each of the information storage capacitive elements of a DRAM, the formation of a through hole for connecting the information storage capacitive element formed over each memory cell selection MISFET and a feeding interconnection is performed in a process different from that for the formation of a through hole for connecting an interconnection of a second wiring layer in a peripheral circuit, which is formed over the information storage capacitive element and an interconnection corresponding to a first wiring layer.

Abstract: A steplike offset between a memory cell array region and a peripheral circuit region, which is caused by a capacitor C, is reduced by an insulating film having a thickness substantially equal to the height of the capacitor C. Wiring or interconnection grooves are defined in the neighborhood of the surface of an insulating film whose surface is flattened by a CMP method. Further, connecting holes are defined in lower portions of the bottom faces of the interconnection grooves respectively. Second layer interconnections containing copper are formed within the interconnection grooves, and connecting portions containing copper are formed within the connecting holes. The second layer interconnections and first layer interconnections are connected to each other by the connecting portions whose lengths are shortened. The second layer interconnections and the connecting portions are integrally formed by a damascene method using the CMP method.

Abstract: In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta2O5 (tantalum oxide) film 46, the portions of bit lines BL and first-layer interconnect lines 23 to 26 of a peripheral circuit which are in contact with at least an underlying silicon oxide film 28 are formed of a W film, the bit lines BL and the interconnect lines 23 to 26 being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines 23 to 26 and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.

Abstract: The present invention relates to a semiconductor device that includes a dynamic memory and logic circuits that are integrated on a single chip and that can avoid noise problems and signal delay. The portion above the memory is shielded with a shielding conductor that is biased to an equipotential. Wirings between logical blocks and bonding pads or between logical blocks are passed over the conductive layer. Wiring for logic circuits can be done in the same metal wiring layer in which the shielding conductor is provided. The shielding conductor can have a mesh-like structure to improve its integrity and wirings can be passed over conductive portions of the shielding layer to be protected from noise. In addition to the dynamic memory, other memories and analog circuits can be used instead of or in combination with the dynamic memory.

Abstract: In order to improve connection reliability of a feeding interconnection connected to an electrode of each of the information storage capacitive elements of a DRAM, the formation of a through hole for connecting the information storage capacitive element formed over each memory cell selection MISFET and a feeding interconnection is performed in a process different from that for the formation of a through hole for connecting an interconnection of a second wiring layer in a peripheral circuit, which is formed over the information storage capacitive element and an interconnection corresponding to a first wiring layer.

Abstract: A steplike offset between a memory cell array region and a peripheral circuit region, which is caused by a capacitor C, is reduced by an insulating film having a thickness substantially equal to the height of the capacitor C. Wiring or interconnection grooves are defined in the neighborhood of the surface of an insulating film whose surface is flattened by a CMP method. Further, connecting holes are defined in lower portions of the bottom faces of the interconnection grooves respectively. Second layer interconnections containing copper are formed within the interconnection grooves, and connecting portions containing copper are formed within the connecting holes. The second layer interconnections and first layer interconnections are connected to each other by the connecting portions whose lengths are shortened. The second layer interconnections and the connecting portions are integrally formed by a damascene method using the CMP method.

Abstract: In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta2O5 (tantalum oxide) film 46, the portions of bit lines BL and first-layer interconnect lines 23 to 26 of a peripheral circuit which are in contact with at least an underlying silicon oxide film 28 are formed of a W film, the bit lines BL and the interconnect lines 23 to 26 being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines 23 to 26 and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.

Abstract: A semiconductor integrated circuit device of the invention is provided with a memory cell array portion and a peripheral circuit portions. In the memory cell array portion, a plurality of plugs which penetrate each of a plurality of interlayer insulating films and the sides of which are almost vertical are directly connected in sequence. In the peripheral circuit portion, a plurality of plugs are mutually connected through contact pads for wiring.

Abstract: A semiconductor integrated circuit apparatus according to the present invention has a capacitor formed in such a manner that a ferroelectric thin film is formed after a MOS transistor has been formed on a substrate thereof, a ferroelectric thin film made of, for example, PbZrTiO.sub.3 or SrTiO.sub.3 or the like is formed into a columnar shape to form electrodes positioned in direct contact with the side wall portions of said columnar ferroelectric thin film and the top portion is removed.

Abstract: A semiconductor device has a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type contacted by respective first and second electrodes. A semi-insulating layer extends between the first and second electrodes and there is a first insulating layer between the semi-insulating layer and the first semiconductor region. The sheet resistivity of the semi-insulating layer varies, and this improves the high breakdown voltage of the p-n junction of the semiconductor device between the first and second semiconductor layers, by acting as a shield for charges included on a passivation insulation layer covering the semi-insulating layer and the first and second electrodes. Third semiconductor regions, with corresponding third electrodes, extend around, and are spaced from, the second semiconductor region.

Abstract: In a plasma processing apparatus which forms a gaseous raw material into a plasma by using electron cyclotron resonance and processes a substrate, leading-edge opening portions of an introduction tube into which a gaseous raw material is introduced are formed in the inner wall surface of the container in such a way that they do not project within the vacuum container. A heater is wound around the introduction pipe so that the opening portions thereof can be heated. With this construction, even if a gaseous raw material which is a liquid or solid at normal temperature and normal pressure is made to flow, the gaseous raw material can be prevented from being liquefied or solidified in the opening portions of the introduction pipe, and the opening portions of the introduction pipe can be prevented from being clogged. In addition, since there are no projections within the vacuum container, the propagation of microwaves is not impeded, making it possible to uniformity process the substrate.

Abstract: A microwave plasma processing apparatus is provided with a vacuum chamber, a substrate holder for mounting a substrate to be processed, a reactive gas feed port, a cleaning gas feed port, a plasma generation device for generating a processing plasma from the reactive gas and a cleaning plasma from the cleaning gas, and a high-frequency electric field application device for applying an electric field having a frequency that allows ions in the cleaning plasma to follow changes in the electric field. The high-frequency electric field application device is activated to apply the electric field to the cleaning plasma so as to remove substances that have been deposited on the surfaces of the vacuum chamber and substrate holder due to the processing of the substrate by the processing plasma, thereby cleaning up the vacuum chamber and substrate holder.

Abstract: A plasma treatment apparatus for forming a thin film on a substrate in a vacuum vessel includes a magnetic field generator which can be positioned inside or outside the vacuum vessel, and a microwave source. The magnetic field strength is controllable such that an electron cyclotron resonance (ECR) area is defined near the substrate. The magnetic field generator can be arranged so that plasma and reactive gas introduction ports are on the microwave introduction side of the ECR area and the substrate is on the opposite side of the ECR area. Alternatively, a gas introduction port can be positioned such that reactive gas is introduced into the ECR area or onto the substrate.

Abstract: A semiconductor integrated circuit apparatus according to the present invention has a capacitor formed in such a manner that a ferroelectric thin film is formed after a MOS transistor has been formed on a substrate thereof, a ferroelectric thin film made of, for example, PbZrTiO.sub.3 or SrTiO.sub.3 or the like is formed into a columnar shape to form electrodes positioned in direct contact with the side wall portions of said columnar ferroelectric thin film, and the top portion is removed.

Abstract: Disclosed are a semiconductor device comprising a semiconductor substrate, a first metal connection layers, a first substrate oxide layer having a specific form, and a second connection pattern layer; a process for producing the device; and a microwave plasma treatment apparatus having gas feed ports in a specific position. The highly reliable semiconductor devices can be produced at a high rate at high yields.

Abstract: The present invention relates to a microwave plasma processing apparatus for processing such as thin film formation, etching, sputtering, and plasma oxidation, etc., on a surface of a processing object by utilizing a high density plasma generated by electron cyclotron resonance. A vacuum vessel of the apparatus, in which a microwave transmitted by a microwave guide is utilized for converting gas supplied to the vacuum vessel to plasma for the plasma processing of the processing object placed in the vacuum vessel, is formed in, such manner that the interior space of the vacuum vessel extends beyond the outer periphery of magnetic field generating coils, and the extended portion of the vessel is provided with a gas outlet for connection with an evacuation apparatus to evacuate the interior of the vacuum vessel to a desired vacuum degree.

Abstract: A plasma processing apparatus performs a sample processing and cleaning processing. The sample processing is carried out by generating a reaction gas plasma within a vacuum vessel of the apparatus using an electron cyclotron resonance excitation. The cleaning processing is carried out to clean the inner wall of the vacuum vessel by generating a cleaning gas plasma within the vacuum vessel. Generation of the cleaning gas plasma takes place by using either one of the following processes:(1) The plasma diameter during the cleaning processing is made larger than that during the sample processing. The end of the plasma during cleaning processing is made to reach the inside wall of the vacuum vessel.(2) The cleaning gas plasma is scanned within the vacuum vessel.

Abstract: In a plasma processing apparatus using ECR, faces in contact with plasma excepting a substance to be processed are covered by an insulating material. By such configuration, discharge caused between the plasma and the substance to be processed in plasma processing is prevented beforehand.